3 Commits

Author	SHA1	Message	Date
Martin Radev	81d95456b9	gpu: nvgpu: Rename PLATFORM_ATOMIC to SYSTEM_COHERENT ... To support current and future usecases, it would be beneficial to select the SYSTEM_COHERENT aperture explicitly. The benefits are: - platform atomic code is cleaned-up. - userspace can select the SYSTEM_COHERENT aperture for any specific usecases. Bug 3959027 Change-Id: I6489ebe87fa75cc760930277bad5e0cacca80eb6 Signed-off-by: Martin Radev <mradev@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2864177 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>	2023-04-21 11:31:53 -07:00
Vedashree Vidwans	2d24298af0	gpu: nvgpu: update nvgpu_pte_dbg_print function ... Currently, nvgpu_pte_dbg_print() overwrites ctag string "ctag=" and only prints ctag number. For example, nvgpu_pte_dbg_print:104 [DBG] vm=3 PTE: i=0 size=8 | GPU 0x1efc000000 phys 0x115a50000 pgsz: 4kb perm=RW kind=0x8 APT=SYSTEM C--V- 1 [0x08000010, 0x115a5007] Update nvgpu_pte_dbg_print function to include ctag string. nvgpu_pte_dbg_print:104 [DBG] vm=3 PTE: i=0 size=8 | GPU 0x1efc000000 phys 0x115a50000 pgsz: 4kb perm=RW kind=0x8 APT=SYSTEM C--V- ctag=1 [0x08000010, 0x115a5007] Jira NVGPU-5489 Change-Id: I2f84f89da685ad6a84534c0bb51e3ca1244b3497 Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2354182 Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Seema Khowala <seemaj@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2020-12-15 14:13:28 -06:00
Vedashree Vidwans	cd7194cbc0	gpu: nvgpu: modify gmmu page table entry functions ... Move below chip agnostic gmmu pte functions to common/mm/gmmu/pte.c. - gmmu_aperture_mask() - pte_dbg_print() Default big page size for all chips is 64K. So, move gp10b_mm_get_default_big_page_size() to common file and rename as nvgpu_gmmu_default_big_page_size(). Modify gv11b_gpu_phys_addr() to use get_iommu_bit() hal. JIRA NVGPU-4666 Change-Id: I512c42723faf2d03e5b367879c9c385dcf52cdc2 Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2329560 Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2020-12-15 14:13:28 -06:00