Commit Graph

8 Commits

Author SHA1 Message Date
Sunny He
959c02d675 gpu: nvgpu: Reorg mm HAL initialization
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
mm sub-module of the gpu_ops struct.

Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.

Jira NVGPU-74

Change-Id: Ieb87a62f047510e51c52e6563d8e3fd5a65b5f28
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1537753
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-08-14 15:55:19 -07:00
Sunny He
f8399cfa55 Revert "gpu: nvgpu: Reorg mm HAL initialization"
Conflicts with gv100 changes

This reverts commit 8d63cd3995.

Change-Id: Ie2f88d281b2b87a9a794d79164a61c4d883626b7
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1537668
Reviewed-by: Shu Zhong <shuz@nvidia.com>
Tested-by: Shu Zhong <shuz@nvidia.com>
2017-08-11 14:57:15 -07:00
Sunny He
8d63cd3995 gpu: nvgpu: Reorg mm HAL initialization
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
mm sub-module of the gpu_ops struct.

Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.

Jira NVGPU-74

Change-Id: I289284e6e528fc7951c959c8765ccf9349eec33b
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1533351
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-08-11 14:16:52 -07:00
Deepak Nibade
6c643bdb5f gpu: nvgpu: remove coherence support from gp10b
We do not support coherence for gp10b, hence clean up related code
Remove API gp10b_mm_phys_addr_translate() and use physical address
instead

Also, since now gp10b_mm_iova_addr() becomes equivalent to
gk20a_mm_iova_addr(), remove gp10b_mm_iova_addr() altogether
We first set gk20a_mm_iova_addr() to get_iova_addr() pointer anyways
so we continue using gk20a version of the API

Jira GPUT19X-17
Bug 1651331
Bug 200283998

Change-Id: Ic1ca198fcde7ddbcd23516bff8a2e65c9eae32b1
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master/r/1512598
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2017-07-07 07:05:38 -07:00
Bharat Nihalani
dfe6493dcb Revert "gpu: nvgpu: fix allocator_init() calls"
This reverts commit 053037f1450d6ba6c5d01abcdcd9b24019ae8c85
since the issue seen with bug 200106514 is fixed with change
http://git-master/r/#/c/752080/.

Bug 200112195

Change-Id: If54eb570fd2ad5de99d180d03d5d90492283fe33
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/752504
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-12-27 15:22:06 +05:30
Deepak Nibade
021748b782 gpu: nvgpu: fix allocator_init() calls
Change for new VA space allocator is being reverted with
http://git-master/r/#/c/749291/ but only for Kernel3.18

In Kernel3.10, we support the new VA allocator

Since we support both the kernel versions as of now,
use a KERNEL_VERSION based mechanism to select
appropriate call

Define new macro NVGPU_USE_NEW_ALLOCATOR for Kernel3.10
where we want to use new allocator

Bug 200106514

Change-Id: I9af26d555278c40e03fe82b0912961a862c8bf55
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/751353
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2016-12-27 15:22:06 +05:30
Deepak Nibade
9f22ad4687 gpu: nvgpu: add get_iova_addr() for gp10b
Add platform specific gp10b_mm_iova_addr() to get
iova/phys address for gp10b

If SMMU is not enabled and IO coherence flag is set,
set 34th bit in the physical address and return the
physical address

If SMMU is enabled, return the iova address

Bug 1605653

Change-Id: I5c91a8c8d85d8a8e422406e3c91fc1dda3cb0870
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/713106
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-12-27 15:22:04 +05:30
Terje Bergstrom
c23f7708ac gpu: nvgpu: gp10b: Define physical address width
GP10B physical address width is 37 bits. Use old width for now,
and add gp10b specific definition. We can switch to new definition
once we've verified them.

Bug 1567274

Change-Id: I33cc1b99f14f1a7ee5f6fe3bd3d8b3126c23ecbe
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/601703
2016-12-27 15:22:02 +05:30