3 Commits

Author	SHA1	Message	Date
David Nieto	fe2b83ef4d	gpu: nvgpu: refactor interrupt handling ... JIRA: EVLR-1004 (*) Refactor the non-stalling interrupt path to execute clear on the top half, so on dGPU case processing of stalling interrupts does not block non-stalling one. (*) Use a worker thread to do semaphore wakeups and allow batching of the non-stalling operations. (*) Fix a bug where some gpus will not properly track the completion of interrupts, preventing safe driver unloads Change-Id: Icc90a3acba544c97ec6a9285ab235d337ab9eefa Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1312796 Reviewed-on: http://git-master/r/1320848 GVS: Gerrit_Virtual_Submit Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>	2017-03-20 06:42:07 -07:00
Mahantesh Kumbar	d37aa77ab5	gpu: nvgpu: Allow enabling/disabling MC interrupt ... Added method to enable/disable MC interrupt by unit Bug 200064127 Change-Id: I89e794d5b69a2a93642e2df437d6744bf595f021 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/661211 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>	2015-03-18 12:12:31 -07:00
Terje Bergstrom	8371833f42	gpu: nvgpu: Per-chip interrupt processing ... Move accesses to MC registers under HAL so that they can be reimplemented per chip. Do chip detection and HAL initialization only once. Bug 1567274 Change-Id: I20bf2f439d267d284bfd536f1a1dfb5d5a2dce4c Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/590385	2015-03-18 12:11:56 -07:00