Commit Graph

21 Commits

Author SHA1 Message Date
Richard Zhao
c30afdce02 gpu: nvgpu: add periodic timer API
move fecs_trace polling from kthread to timer API.

Jira GVSCI-10883

Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: I224754b7205f1d0eefdc19a73a98f42e4d3e9d0e
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2700601
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-by: Aparna Das <aparnad@nvidia.com>
GVS: Gerrit_Virtual_Submit
2022-05-02 23:16:44 -07:00
Dinesh T
358f62a9d7 gpu: nvgpu: Add compression for safety
This is adding compression support for qnx-safety by
- Adding the compression related files under FUSA.
- Adding new posix contig-pool.c for user space compilation.

Bug 3426194

Change-Id: Ib3c8e587409dc12099c1196f55a87858d4dc520e
Signed-off-by: Dinesh T <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2652963
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2022-03-15 17:30:57 -07:00
scottl
3cd256b344 gpu: nvgpu: add linux REMAP support
Add REMAP ioctl and accompanying support to the linux nvgpu driver.

REMAP support provides per-page control over sparse VM areas using the
concept of a virtual memory pool.

The REMAP ioctl accepts a list of operations (each a map or unmap) that
modify the VM area pages tracked by the virtual mmemory pool.

Inclusion of REMAP support in the nvgpu build is controlled by the new
CONFIG_NVGPU_REMAP flag.  This flag is enabled by default for linux builds.
A new NVGPU_GPU_FLAGS_SUPPORT_REMAP characteristics flag is added for use
in detecting when REMAP support is available.

When a VM allocation tagged with NVGPU_VM_AREA_ALLOC_SPARSE is made the
base virtual memory pool resources are allocated.  Per-page resources are
later allocated when the NVGPU_AS_IOCTL_REMAP ioctl is issued.  All REMAP
resources are released when the corresponding VM area is freed.

Jira NVGPU-6804

Change-Id: I1f2cdc0c06c1698a62640c1c6fbcb2f9db24a0bc
Signed-off-by: scottl <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2542178
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-06-28 22:39:06 -07:00
Richard Zhao
ab6d4fa543 gpu: nvgpu: create common sim reg accessors
sim reg accessors is common after it moved to use os abstract layer reg
accessors.

Bug 2999617

Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: I1c0ff7ca1724cde09dd845c077763709ea2ef915
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2517383
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-04-28 19:15:31 -07:00
Alex Waterman
5f0fdf085c nvgpu: unit: Add new mock register framework
Many tests used various incarnations of the mock register framework.
This was based on a dump of gv11b registers. Tests that greatly
benefitted from having generally sane register values all rely
heavily on this framework.

However, every test essentially did their own thing. This was not
efficient and has caused a some issues in cleaning up the device and
host code.

Therefore introduce a much leaner and simplified register framework.
All unit tests now automatically get a good subset of the gv11b
registers auto-populated. As part of this also populate the HAL with
a nvgpu_detect_chip() call. Many tests can now _probably_ have all
their HAL init (except dummy HAL stuff) deleted. But this does
require a few fixups here and there to set HALs to NULL where tests
expect HALs to be NULL by default.

Where necessary HALs are cleared with a memset to prevent unwanted
code from executing.

Overall, this imposes a far smaller burden on tests to initialize
their environments.

Something to consider for the future, though, is how to handle
supporting multiple chips in the unit test world.

JIRA NVGPU-5422

Change-Id: Icf1a63f728e9c5671ee0fdb726c235ffbd2843e2
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2335334
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2020-12-15 14:13:28 -06:00
ajesh
057d746690 gpu: nvgpu: make circ_buf and log2 as safe
Mark circ_buf and log2 units under posix as safe units.

Jira NVGPU-4417

Change-Id: Ifd486242f94884f9696f18af0412b17c2517f21e
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2289637
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2020-12-15 14:13:28 -06:00
Vaibhav Kachore
bbb63c0a8c gpu: nvgpu: remove "trace/events/gk20a.h" from QNX build
- "include/trace/events/gk20a.h" file was having GPL2 license
(which should not used for QNX code). This file was used for
compiling linux userspace driver("libnvgpu-drv.so") and was used for
unit testing on QNX.
- This patch removes stubs in "include/trace/events/gk20a.h" file.
(which were used for linux userspace driver.)
- For QNX driver, "nvgpu_rmos/trace/events/gk20a.h" was used.
This patch moves that file to "include/nvgpu/posix/trace_gk20a.h" and
does relevant license change. This same file will be used for linux
userspace driver.
- This patch also creates a new file "include/nvgpu/trace.h" which
selects proper trace file depending on the config.

Bug 2802414

Change-Id: Icdfb251e5698073f986753a969e804161af3ecc5
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2286388
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2020-12-15 14:13:28 -06:00
ajesh
129b0a28d4 gpu: nvgpu: make sort as non safe unit
Mark sort unit as non safe as the functionality is not
used by any of the safe files.

Jira NVGPU-4903

Change-Id: Iba5475d91bae217657a03b4b1cb20ca7e2b549cd
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2283546
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2020-12-15 14:10:29 -06:00
Petlozu Pravareshwar
b4029e9bfa gpu: nvgpu: posix: Make queue.c as a safe file
Make Queue.c as a safe file in YAML because Queue.c file APIs
are used by SDL unit.

JIRA NVGPU-2679

Change-Id: Ia1a69e0f09addf70dfedb52516ceb7642bd35c6e
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2280026
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2020-12-15 14:10:29 -06:00
Thomas Fleury
dd8be7cb82 gpu: nvgpu: posix: add os_priv for channel
Add os_priv for channel, to store error notifier.
Updated the following functions to use error notifier
in ch->os_priv, when present:
- nvgpu_set_err_notifier_locked
- nvgpu_set_err_notifier
- nvgpu_set_err_notifier_if_emtpy
- nvgpu_is_err_notifier_set

Jira NVGPU-4387

Change-Id: I9718d045fc780f721548201981b038de46b36a7e
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2248160
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2020-12-15 14:10:29 -06:00
Debarshi Dutta
4cc1fa1a0b gpu: nvgpu: construct initial utf for sync unit.
This patch constructs the initial setup for sync unit.
There are three simple tests currently. The first test inits the
environment necessary such as regspace init, hal init. The second
step simply fails the creation of the sync and the last test is meant
as a deinit step.

JIRA NVGPU-913

Change-Id: I1db72d9833c3c4bc3c3903a7d81cce06e9983509
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2248493
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2020-12-15 14:10:29 -06:00
Petlozu Pravareshwar
8ee9bdd8c8 gpu: nvgpu: posix: Move nvgpu queue APIs to posix
Currently nvgpu queue APIs are in nvgpu_rmos folder
but they can be moved to Posix layer. This change adds
the queue APIs to posix layer and the same will get deleted
from the nvgpu_rmos folder.

JIRA NVGPU-2679

Change-Id: I1d33c9f8eeae5fcb8e628b755e788d0be6310e47
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2229355
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2020-12-15 14:10:29 -06:00
Vedashree Vidwans
d6fc9d176e gpu: nvgpu: fix MISRA 17.1 in timeout_expired_msg
MISRA rule 17.1 forbids use of stdarg.h features defined for variable
arguments. This patch creates timers.h header for posix and QNX to
change nvgpu_timeout_expired_msg() to macro definition.

Jira NVGPU-4075

Change-Id: I8167f0ff7fdfb74adbbbed9c3021a9df2ad6401b
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2200885
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2020-12-15 14:05:52 -06:00
Vedashree Vidwans
7c98fbba42 gpu: nvgpu: fix MISRA 17.1 in logging functions
MISRA Rule 17.1 forbids use of stdarg.h features which are defined for
variable arguments.
This patch modifies logging macros to use slogf function for QNX builds.
This avoids use of variable argument functions used for formatting log
message.

Jira NVGPU-4075

Change-Id: I5b6bb1107a7e431afaa960003858193a477b2ee6
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2192016
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2020-12-15 14:05:52 -06:00
Prateek sethi
7d8757b9a4 gpu: nvgpu: add fault injection for file ops
This creates wrappers for read and fstat and adds the ability to
enable fault injection for these calls.

Jira NVGPU-2678

Change-Id: I8bdf38e7044aef5bb676b3c35dabccb0daf4f334
Signed-off-by: Prateek sethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2171299
Reviewed-by: Dinesh T <dt@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2020-12-15 14:05:52 -06:00
Vedashree Vidwans
7bc3cdcf95 gpu: nvgpu: use vpr resize enabled API
This patch adds nvgpu API in linux and posix to query vpr resize.
The new API nvgpu_is_vpr_resize_enabled() is used in
nvgpu_submit_channel_gpfifo().
Previously, if non-deterministic channel has timeout disabled and
GPU cannot railgate on some platform, then channel doesn't power ref
count and results in video freeze. To resolve non-determinstic channel
job tracking needs to be enabled if vpr resize is supported or if GPU
can railgate.

Bug 200532122

Change-Id: Icfbff6253762b195b2f5955749343974b1a7a269
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2171093
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-08-28 14:24:19 -07:00
Shashank Singh
627a933da5 gpu: nvgpu: Unify posix sort unit with qnx
-Unify sort function with qnx as qsort is posix compliant.
-Update yaml accordingly.

Jira NVGPU-3625

Change-Id: I982570bccb3bc8720596bfacf48eb17a0fca2ddf
Signed-off-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2134355
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-06-13 06:42:07 -07:00
Vinod G
8db47e6f51 gpu: nvgpu: Add utils.h to YAML arch
Move all definitions and functions other than type defines from types.h
to new header utils.h for posix.
Update files that use functions and defintions from utils.h

Jira NVGPU-3411

Change-Id: I6d9b165f882282450d4b35f4d6a0200effe76791
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130529
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-06-07 17:05:41 -07:00
Thomas Fleury
0a2bac5974 gpu: nvgpu: unit: add io callbacks for tegra fuses
Remove WAR to set FMODEL during gv11b_init_hal.
Instead, add io callbacks for tegra fuses, and return
GCPLEX_CONFIG_WPR_ENABLED_MASK for FUSE_GCPLEX_CONFIG_FUSE_0.

Jira NVGPU-3476

Change-Id: I0739d66668b0f5c6658346b67bc368682edda4da
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120680
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-24 19:05:47 -07:00
Deepak Nibade
dfdd05a3d6 gpu: nvgpu: disable fecs trace support for safety builds
Compile all files with fecs trace support only if flag
NVGPU_FECS_TRACE_SUPPORT is set

remove CONFIG_GK20A_CTXSW_TRACE checks from within the files

add POSIX file for fecs trace support for compilation with
make command

Jira NVGPU-3414

Change-Id: I205e3494ce94138ab6c6fccf7fbcefc41f953c77
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120276
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-21 10:36:04 -07:00
Alex Waterman
6efe02f776 gpu: nvgpu: Add YAML arch to linux-nvgpu
Add the YAML arch to the linux-nvgpu repo so that the arch and source
code can be kept entirely in sync.

When the YAML was in a separate repo it was too difficult to keep things
in sync. Based on this work the next steps are:

  1. Gate compilation on no sources issues (missing or orphan source
     files.
  2. Perhaps use the arch to generate the Makefile.sources files.

JIRA NVGPU-3074
JIRA NVGPU-3075
Bug 2587555

Change-Id: Ic62be3e5e7ea1fb61ea50a2d611f905fa574988f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2113154
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-13 10:47:44 -07:00