Commit Graph

6 Commits

Author SHA1 Message Date
Philip Elcan
cf8707e2b3 gpu: nvgpu: mm: add hal to get max page table levels
Add a HAL API to get the maximum page table levels for the current
hardware.

JIRA NVGPU-3489

Change-Id: I1635ca576f3db461afb8e4e46db1e8912bcfdcd6
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2224449
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2020-12-15 14:10:29 -06:00
Scott Long
c6b6c9b3e2 gpu: nvgpu: mm: remove misra rule 8.11 violations
Eliminate Advisory Rule 8.11 violations in gmmu_gk20a.h by
removing extern declarations of gk20a_mm_levels_64k[] and
gk20a_mm_levels_128k[].

Advisory Rule 8.11 states when an array with external linkage
is declared, its size should be explicitly specified.

Jira NVGPU-3178

Change-Id: I452a571e0561edbd9f8cd856775563587c201d40
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2162273
GVS: Gerrit_Virtual_Submit
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2019-07-30 09:56:36 -07:00
Vedashree Vidwans
afae2efc23 gpu: nvgpu: fix MISRA errors in nvgpu.hal.mm
Rule 8.6 requires each identifier with external linkage to have exactly
one external definitions.
Rule 10.x necessitates operands to have essential type; left and right
operands should be of same width and type.
Rule 14.3 doesn't allow controlling expressions to be invariant;
ensuring that all conditions are possible.

Jira NVGPU-3858

Change-Id: I043a3836c4a2cb9c5a52d3053516c517389f55a2
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2162295
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Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
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2019-07-29 12:45:40 -07:00
Philip Elcan
66c79f3bb3 gpu: nvgpu: mm: use u64 for get_mmu_levels()
Change the big_page_size parameter for the HAL API get_mmu_levels from
u32 to u64. This eliminates a CERT-C INT31 violation in page_table.c for
casting without checking the value.

JIRA NVGPU-3515

Change-Id: If001407666acd21733017f420e615ae6bd6d929c
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2125026
Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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2019-05-29 12:59:40 -07:00
Alex Waterman
6c2c4181ae gpu: nvgpu: Create hal.mm.mm for misc MM HALs
There are many miscellaneous HALs for various MM related functionality.
This patch aims to migrate all the remaining MM code from the <chip>/
mm_<chip>.[ch] files in HAL files under hal/.

Much of this is fairly straightforward copy/paste and updates to the
HAL init files.

The exception to that is the move of the left over gv11b MMU fault
handling code in mm_gv11b.c. Having both a hal/mm/mm/mm_gv11b.c and
a gv11b/mm_gv11b.c file causes tmake to choke so the gv11b/mm_gv11b.c
file was moved to gv11b/mmu_fault_gv11b.c. This will be cleaned up in
a subsequent patch.

JIRA NVGPU-2042

Change-Id: I12896de865d890a61afbcb71159cff486119ffb8
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109050
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2019-05-01 15:06:57 -07:00
Alex Waterman
efbe371fd5 gpu: nvgpu: Create hal/mm/gmmu and move gk20a GMMU code
Make a hal/mm/gmmu sub-unit for the GMMU HAL code. Also move the
gk20a specific HAL code there. gp10b will happen in the next patch.

This change also updates all the GMMU related HAL usage, of which
there is quite a bit. Generally the only change is a .gmmu needs to
be inserted into the HAL path. Each HAL init was also updated.

JIRA NVGPU-2042

Change-Id: I6c46bdfddb8e021f56103d9457fb3e2a226f8947
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2099693
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2019-04-23 12:45:54 -07:00