Commit Graph

1526 Commits

Author SHA1 Message Date
David Nieto
74fe1caa2b gpu: nvgpu: Add refcounting to driver fds
The main driver structure is not refcounted properly,
so when the driver unload, file desciptors associated to the
driver are kept open with dangling references to the main object.

This change adds referencing to the gk20a structure.

bug 200277762
JIRA: EVLR-1023

Change-Id: Id892e9e1677a344789e99bf649088c076f0bf8de
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1317420
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2017-03-20 16:39:55 -07:00
David Nieto
469308beca gpu: nvgpu: fix arbiter teardown on PCI
The driver is not properly tearing down the arbiter on the PCI driver
unload. This change makes sure that the workqueues are drained before
tearing down the driver

bug 200277762
JIRA: EVLR-1023

Change-Id: If98fd00e27949ba1569dd26e2af02b75897231a7
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1320147
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-03-20 16:39:50 -07:00
Seema Khowala
50f371f891 gpu: nvgpu: add fifo ops for intr_0_error_mask
This change is required to support t19x mmu fault

Change-Id: I3953dcf02c71ace606ba81896e56ea98683eb2ca
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1313482
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2017-03-20 16:39:49 -07:00
Peter Daifuku
38d90b6092 gpu: nvgpu: del channel job before fence is closed
In gk20a_channel_clean_up_jobs, move removal of job from channel's job list
to before fences are cleaned up; this will prevent gk20a_channel_abort from
asynchronously trying to dereference an already freed job.

Bug 1844305
JIRA EVLR-849

Change-Id: I1ba05237aa74be1350007630bfa5eba9988f859a
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
(cherry picked from commit 2a9ce58b1b318b95ecfcdf78462f918d090eab99)
Reviewed-on: http://git-master/r/1319026
(cherry picked from commit 990f070b0a363159ce1b21f936b7512f469018ca)
Reviewed-on: http://git-master/r/1321624
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-03-17 10:56:34 -07:00
Terje Bergstrom
ca762e4220 gpu: nvgpu: Move all FB programming to FB HAL
Move all programming of FB to fb_*.c files, and remove the inclusion
of FB hardware headers from other files.

TLB invalidate function took previously a pointer to VM, but the new
API takes only a PDB mem_desc, because FB does not need to know about
higher level VM.

GPC MMU is programmed from the same function as FB MMU, so added
dependency to GR hardware header to FB.

GP106 ACR was also triggering a VPR fetch, but that's not applicable
to dGPU, so removed that call.

Change-Id: I4eb69377ac3745da205907626cf60948b7c5392a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1321516
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2017-03-17 08:44:03 -07:00
Terje Bergstrom
589d6385b1 gpu: nvgpu: Implement get_rate/set_rate as GPU op
Move clock APIs from gk20a_platform to gpu_ops. At the same time
allow use of internal get_rate/set_rate for querying both GPCCLK
and PWRCLK on iGPU.

At the same time we can replace calls to clk framework with the
new HAL and drop direct dependency to clk framework.

gp10b ops were replaced as a whole at HAL initialization. That
replaces anything set in platform probe stage, so reduce that to
touch only clock gating regs.

Change-Id: Iaf219b1f000d362dbf397d45832f52d25463b31c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1300113
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2017-03-16 11:48:29 -07:00
Terje Bergstrom
686c3b701f gpu: nvgpu: Move platform files to Tegra Linux
Platform files are used for adding code to probe for Tegra Linux
platform. Move the files to Tegra Linux directory to make this
clear.

Change-Id: Ida66af835688325f095260c618dad90395851267
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1300112
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
2017-03-16 11:48:24 -07:00
Terje Bergstrom
2821eb31e2 gpu: nvgpu: Rename clk->get_rate to measure_freq
get_rate is already used for call-back that queries the last set
clock rate. This instance of get_rate actually measures the frequency
so renaming it to measure_freq.

At the same time modify to use hertz instead of megahertz. We use
fractional megahertz already in GPU.

Change-Id: I387473d6a6cbf3bb9b9e5a909677a1a725403c32
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1300111
Reviewed-by: Alex Waterman <alexw@nvidia.com>
2017-03-16 11:48:24 -07:00
Konsta Holtta
7fd72e3135 gpu: nvgpu: cancel vidmem worker only if supported
Cancel the vidmem.clear_mem_worker during suspend only if vidmem is
enabled via kernel config. Otherwise it's not initialized.

Bug 1853519

Change-Id: If88c756ae14f348eddda01218fa218480217388c
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1321118
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-03-16 09:17:22 -07:00
Konsta Holtta
dd0f3a061b gpu: nvgpu: avoid double-free of incr cmd
The call site (gk20a_submit_prepare_syncs) owns the incr_cmd buffer
passed to __gk20a_channel_semaphore_incr. Delete the free in the error
path of the latter case to avoid freeing the same buffer twice.

Bug 1853519

Change-Id: I9b90ce7ebb17ac63992938c7f9fe90bbd139f85f
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1321117
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-03-16 09:17:22 -07:00
Seema Khowala
93ba29c5b5 gpu: nvgpu: channel_from_inst_ptr renamed and made non static
required to support t19x mmu fault

Change-Id: Ibe621d924717696a359d7e2065beb6501a9f9b5e
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1315928
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2017-03-14 15:26:56 -07:00
Terje Bergstrom
85cb10c313 gpu: nvgpu: Remove unused function gk20a_get_phys_from_iova
Remove unused function gk20a_get_phys_from_iova. At the same time
remove the #include for iommu.h, which was only needed by this
function.

Change-Id: Ia858b0ad5fe7e423d650aa9f82e430f419f2a492
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1319070
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2017-03-14 11:47:17 -07:00
Terje Bergstrom
503a5e6826 gpu: nvgpu: Do not use pm_runtime calls directly
mm_gk20a.c had direct calls to pm_runtime_put_noidle(). Replace
them with calls to wrapper gk20a_idle_nosuspend() to prevent
unnecessary dependencies to Linux.

Change-Id: Iaf8b9255750be2f3e1aa39587c1a4a3cbeacc67f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1319069
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2017-03-14 11:47:11 -07:00
Rajkumar Kasirajan
e4a131a98d Revert "gpu: nvgpu: change stall intr handling order"
This reverts commit 35f0cf0efe as
it caused lp0 suspend/resume failure.

Bug 1886110

Change-Id: Ib62207650344180361b6529f716f77b84528cd56
Signed-off-by: Rajkumar Kasirajan <rkasirajan@nvidia.com>
Reviewed-on: http://git-master/r/1317986
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2017-03-14 11:47:05 -07:00
Deepak Nibade
bf717d6273 gpu: nvgpu: check return value of mutex_init for channel/TSG
- check return value of nvgpu_mutex_init for all the mutexes
  of a channel and TSG
- add corresponding nvgpu_mutex_destroy calls

Jira NVGPU-13

Change-Id: Iba3a5f8bc2261ec684b300dd4237ab7d22fa3630
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1317139
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2017-03-14 11:46:58 -07:00
Deepak Nibade
9efadcdfc0 gpu: nvgpu: check return value of mutex_init for semaphores
- check return value of nvgpu_mutex_init for semaphores
- add corresponding nvgpu_mutex_destroy calls

Jira NVGPU-13

Change-Id: I5404dbd29e3fce29f1a445eb2e6ce8e1d1b616c4
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1317138
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Navneet Kumar <navneetk@nvidia.com>
2017-03-14 11:46:53 -07:00
Deepak Nibade
7dfc81d663 gpu: nvgpu: check return value of mutex_init in fecs_trace_gk20a.c
- check return value of nvgpu_mutex_init in fecs_trace_gk20a.c
- add corresponding nvgpu_mutex_destroy calls

Jira NVGPU-13

Change-Id: I1fe9dd31bbc084bf66dd73dd26b395d898fde9c4
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1317136
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Navneet Kumar <navneetk@nvidia.com>
2017-03-14 11:46:53 -07:00
Deepak Nibade
d6e46c4d37 gpu: nvgpu: check return value of mutex_init in dbg_gpu_gk20a.c
- check return value of nvgpu_mutex_init in dbg_gpu_gk20a.c
- add corresponding nvgpu_mutex_destroy calls

Jira NVGPU-13

Change-Id: I153ef2dd17d0fe17b3f38f6fa7e165d1aeaa2a42
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1317135
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Navneet Kumar <navneetk@nvidia.com>
2017-03-14 11:46:53 -07:00
Deepak Nibade
ce810756ba gpu: nvgpu: check return value of mutex_init in ctxsw_trace_gk20a.c
- check return value of nvgpu_mutex_init in ctxsw_trace_gk20a.c
- add corresponding nvgpu_mutex_destroy calls

Jira NVGPU-13

Change-Id: I7075c6f742dba7ad4c559fedb80a3a96e824db56
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1317134
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Navneet Kumar <navneetk@nvidia.com>
2017-03-14 11:46:53 -07:00
Cory Perry
de568db9de gpu: nvgpu: fix suspending all SMs
In gk20a_suspend_all_sms(), we currently loop
over all GPCs and then loop over all TPCs in inner
loop
But this is incorrect and leads to SM with
invalid GPC,TPC ids

Fix this by looping over number of TPCs in each
GPC in inner loop

Also, fix gk20a_gr_wait_for_sm_lock_down() as
per below
- we right now wait infinitely for SM to lock down
- restrict this wait with a timeout on silicon
  platforms
- return ETIMEDOUT instead of EAGAIN
- add more debug prints with additional data
  for SM lock down failures

Bug 200258704

Change-Id: Id6fe32e579647fd8ac287a4b2ec80cbf98791e0d
Signed-off-by: Cory Perry <cperry@nvidia.com>
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1316471
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2017-03-14 11:46:52 -07:00
David Nieto
403874fa75 gpu: nvgpu: refactor interrupt handling
JIRA: EVLR-1004

(*) Refactor the non-stalling interrupt path to execute clear on the
top half, so on dGPU case processing of stalling interrupts does not
block non-stalling one.
(*) Use a worker thread to do semaphore wakeups and allow batching of
the non-stalling operations.
(*) Fix a bug where some gpus will not properly track the completion
of interrupts, preventing safe driver unloads

Change-Id: Icc90a3acba544c97ec6a9285ab235d337ab9eefa
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1312796
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Lakshmanan M <lm@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Navneet Kumar <navneetk@nvidia.com>
2017-03-14 11:46:38 -07:00
Seema Khowala
4deb494ad1 gpu: nvgpu: debug dump enablement for t19x
Fifo ops added for dumping channel & ramfc status
and pbdma & engine status.


Change-Id: Icc739f4f05f0864721954489517fefdfa2fa608a
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1302369
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2017-03-09 12:23:29 -08:00
Thomas Fleury
6c35cebdcb gpu: nvgpu: vgpu: suspend/resume contexts
Add ability to suspend/resume contexts for a debug session
(NVGPU_DBG_GPU_IOCTL_SUSPEND_RESUME_CONTEXTS), in virtualized
case:
- added hal function to resume contexts.
- added vgpu support for suspend contexts, i.e. build a list
of channel ids, and send TEGRA_VGPU_CMD_SUSPEND_CONTEXTS
- added vgpu support for resume contexts, i.e. build a list
of channel ids, and send TEGRA_VGPU_CMD_RESUME_CONTEXTS

Bug 1791111

Change-Id: Icc1c00d94a94dab6384ac263fb811c00fa4b07bf
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1294761
(cherry picked from commit d17a38eda312ffa92ce92e5bafc30727a8b76c4e)
Reviewed-on: http://git-master/r/1299059
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Cory Perry <cperry@nvidia.com>
Tested-by: Cory Perry <cperry@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-03-09 10:44:55 -08:00
Richard Zhao
bc47d82229 gpu: nvgpu: add NVGPU_GPU_FLAGS_SUPPORT_MAP_COMPBITS
native gpu driver supports map compbits but vgpu does not.

Bug 1778448
Bug 200275051
JIRA VFND-3513

Change-Id: I433a6f8631b495875ba899af9609203ab36187ef
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1314065
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2017-03-08 11:35:24 -08:00
David Nieto
b9feba6efc gpu: nvgpu: in-kernel kickoff profiling
Add a debugfs interface to profile the kickoff ioctl
it provides the probability distribution and separates the information
between time spent in: the full ioctl, the kickoff function, the amount
of time spent in job tracking and the amount of time doing pushbuffer
copies

JIRA: EVLR-1003

Change-Id: I9888b114c3fbced61b1cf134c79f7a8afce15f56
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1308997
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-03-07 13:42:28 -08:00
Seema Khowala
3b0e010d14 gpu: nvgpu: add fifo ops for *client_type_gpc_v
*client_type_gpc_v is different for t19x

Change-Id: Ic8f8eff2d98138a877ef95c6f7f40226f0d61a61
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1313436
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2017-03-07 02:35:01 -08:00
Vijayakumar
b0973391d0 gpu: nvgpu: add pmu trace support for dgpus
1) Trace buffer allocation now calls generic gmmu alloc/map.
  so for dGPUs they are allocated in vidmem and iGPUs they
are allocated in sysmem

2) Use pmu surface mechanism to setup trace buffer params as
dGPU binaries follow falcon memory structure to get mem surface
params

3) Fix minor coverity issue by removing unnecessary overwrite
of count variable in trace print function

JIRA DNVGPU-217

Coverity ID 2431386

Change-Id: I2ae49a4e0450481cde2a778447c270a796681dad
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1312404
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2017-03-07 00:10:50 -08:00
Seema Khowala
35f0cf0efe gpu: nvgpu: change stall intr handling order
-Handle pbus and priv stall interrupts first.
 In general critical interrupts should be
 handled before any other non critical ones.

-Dump info enabled with gpu_dbg_intr if priv_ring
 interrupt is flagged by fmodel.

JIRA NVGPU-25

Change-Id: Iee767d8c9c933ceb57532c1b5a7fd7812daf1b6d
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1311273
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-03-07 00:10:44 -08:00
Terje Bergstrom
d6ff5ef649 gpu: nvgpu: Disable trace_printk use by default
trace_printk() does an extra stringify operation before calling
do_trace_printk(). The string ends up unused. This has an impact
to kernel even if we never end up using trace_printk().

Disable use of trace_printk() and introduce a Kconfig option for
re-enabling it.

Change-Id: I2e1014f5231f2089d7dc3cb2539e3eb5f4d58361
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1295298
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2017-03-07 00:10:41 -08:00
Alex Waterman
707ea45e0f gpu: nvgpu: kmem abstraction and tracking
Implement kmem abstraction and tracking in nvgpu. The abstraction
helps move nvgpu's core code away from being Linux dependent and
allows kmem allocation tracking to be done for Linux and any other
OS supported by nvgpu.

Bug 1799159
Bug 1823380

Change-Id: Ieaae4ca1bbd1d4db4a1546616ab8b9fc53a4079d
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1283828
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2017-03-03 10:34:48 -08:00
Alex Waterman
3966efc2e5 gpu: nvgpu: Give nvgpu_kalloc a less generic name
Change nvgpu_kalloc() to nvgpu_big_[mz]alloc(). This is necessary
since the natural free function name for this is nvgpu_kfree() but
that conflicts with nvgpu_k[mz]alloc() (implemented in a subsequent
patch).

This API exists becasue not all allocation sizes can be determined
at compile time and in some cases sizes may vary across the system
page size. Thus always using kmalloc() could lead to OOM errors due
to fragmentation. But always using vmalloc() is wastful of memory
for small allocations. This API tries to alleviate those problems.

Bug 1799159
Bug 1823380

Change-Id: I49ec5292ce13bcdecf112afbb4a0cfffeeb5ecfc
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1283827
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2017-03-03 10:34:43 -08:00
Alex Waterman
76b78b6fdc gpu: nvgpu: Remove nvgpu_gpuid_t18x.h
Remove nvgpu_gpuid_t18x.h since this file is now visible. Migrate
the relevant definitions and defines into their expected places and
make the code use the real defines. No longer is hiding t18x specific
stuff necessary.

Bug 1799159

Change-Id: I47fa2392e46fdb7aacc70aeb0cc8c3f5ca0dc22f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1300976
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2017-03-02 18:48:41 -08:00
vishnu Reddy
f9b2c30b36 gpu: nvgpu: Add and move FECS trace flag
Added fecs trace characteristic flag to vgpu to determine for
platform support

Also moved fecs flag from ctxsw init to fecs init for native linux.
This makes flag init uniform across both platforms.

JIRA EVLR-993

Change-Id: Id62f31954cb5d7028ef01a199548f5f908b51eb0
Signed-off-by: Vishnu Reddy Mandalapu <vmandalapu@nvidia.com>
Reviewed-on: http://git-master/r/1305045
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2017-03-02 18:15:47 -08:00
Konsta Holtta
f1072a28be gpu: nvgpu: add worker for watchdog and job cleanup
Implement a worker thread to replace the delayed works in channel
watchdog and job cleanups. Watchdog runs by polling the channel states
periodically, and job cleanup is performed on channels that are appended
on a work queue consumed by the worker thread. Handling both of these
two in the same thread makes it impossible for them to cause a deadlock,
as has previously happened.

The watchdog takes references to channels during checking and possibly
recovering channels. Jobs in the cleanup queue have an additional
reference taken which is released after the channel is processed. The
worker is woken up from periodic sleep when channels are added to the
queue.

Currently, the queue is only used for job cleanups, but it is extendable
for other per-channel works too. The worker can also process other
periodic actions dependent on channels.

Neither the semantics of timeout handling or of job cleanups are yet
significantly changed - this patch only serializes them into one
background thread.

Each job that needs cleanup is tracked and holds a reference to its
channel and a power reference, and timeouts can only be processed on
channels that are tracked, so the thread will always be idle if the
system is going to be suspended, so there is currently no need to
explicitly suspend or stop it.

Bug 1848834
Bug 1851689
Bug 1814773
Bug 200270332
Jira NVGPU-21

Change-Id: I355101802f50841ea9bd8042a017f91c931d2dc7
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1297183
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2017-03-02 17:51:03 -08:00
Seema Khowala
0c155313e7 gpu: nvgpu: use litter val for pbdma/eng *status__size*
fifo_pbdma_status__size_1_v() and fifo_engine_status__size_1_v()
are not same for all gpus. Use litter value to calculate chip
specific fifo*status__size_1(v)

JIRA GV11B-45

Change-Id: I3d3d45bf79d15e14739fcc18cb1ca987669d5c11
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1312688
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-03-02 15:05:28 -08:00
Terje Bergstrom
b71fa9289d gpu: nvgpu: Do not bind FECS trace on VPR channels
VPR channels can access VPR, and writing to FECS buffer outside of
VPR causes a region violation.

Bug 1877511

Change-Id: Ida466c81e928d1f67bf1b0e7dd6afb799c1ab2f6
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1312759
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Tested-by: Season Li <seasonl@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
2017-03-02 10:43:40 -08:00
seshendra Gadagottu
f8ec82237e gpu: nvgpu: check for pmu enable
Check for pmu enable, before calling pmu_destrory().

Change-Id: I64c5071ed69b6b50140e46da48a2b165c1f7ba02
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1313391
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-03-02 10:14:30 -08:00
Seema Khowala
3c3f947cf4 gpu: nvgpu: add fifo ops for *data_fault_id_enum_v
generated hw header for top_device_info_data_fault_id_enum_v
is different between legacy chips and t19x

JIRA GV11B-7

Change-Id: I877e88a5b1b1f3f41bc72b895536f4a01b4fbd4e
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1313384
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2017-03-02 08:53:38 -08:00
Seema Khowala
0aafa9e279 gpu: nvgpu: gm20b: add gr ops for load tpc mask
gr_fe_tpc_fs_r addr is different for t19x

Change-Id: I9868fcaf94d063753c4ecf1970b53374cb67b380
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1310326
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-03-02 08:53:32 -08:00
Deepak Nibade
64e1782aee gpu: nvgpu: optimize duplicate buffer lookup in case of fixed offsets
In gk20a_vm_map_duplicate_locked(), we always do a linear search
in rb-tree to find a duplicate entry of the buffer

In case NVGPU_AS_MAP_BUFFER_FLAGS_FIXED_OFFSET is set, we first
traverse whole rb-tree linearly and then compare offset_align
with the address searched from rb-tree

If size of rb-tree is very large this linear lookup takes upto
7mS and causes huge delays

Hence in case of NVGPU_AS_MAP_BUFFER_FLAGS_FIXED_OFFSET, we can
use offset_align to perform a binary search on rb-tree and then
verify that dmabuf and kind match with the node obtained from
the search
This saves a lot of time per-lookup

Bug 1874516

Change-Id: Ia4924b64d66e586c14341ae2e2283beac394bf6f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1309343
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-03-02 07:53:55 -08:00
Thomas Fleury
09504cdbc3 gpu: nvgpu: remove clock domain aliases
Remove MCLK and GPCCLK domain aliases, now that userspace
has swithed to new enumerations.

Jira DNVGPU-211

Change-Id: I2af2fd67dbed47088d7161ba0605e13dd7c674a5
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1292609
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
2017-03-02 02:03:35 -08:00
Seema Khowala
0a3e5941ff gpu: nvgpu: add pbdma and eng bitmask for runlists
-Init pbdma and engine bit mask per runlist.
-Organize debug info to print supported pbdma instances
 for particular runlist.

JIRA GV11B-3

Change-Id: Ie34dd98ccbe2c779ca1c795855c2a7df4abd2715
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1309706
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2017-02-27 10:13:22 -08:00
Deepak Goyal
d6e40fc07a nvgpu: gpu: pmu: Use pmu ops to call pmu_reset().
In this patch hard coded function calls for PMU
reset are replaced by PMU ops.

Change-Id: I266c43e3540163a133895244dcf91169116812f5
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: http://git-master/r/1303757
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2017-02-23 21:33:33 -08:00
Mahantesh Kumbar
9c68af58a9 gpu: nvgpu: ACR interface headers reorganization
-Moved ACR interface headers from acr_gm20b.h/acr_gp106.h to
Its specific header files under “drivers/gpu/nvgpu/include/nvgpu/acr/”
Folder.

- nvgpu_acr.h - Top-level header-file which include ACR interfaces
headers & defines required to communicate with ACR, including this
header file is good to get access into ACR interface & made changes
accordingly,

-Deleted acr.h & acr_t18x.h as not required anymore
& removed its include from dependent files.

Jira NVGPU-19

Change-Id: Ie404043cfe1ab32404eb63a43831f470d8436324
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1304748
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2017-02-23 01:04:48 -08:00
Deepak Nibade
8cdb91c527 gpu: nvgpu: remove use of DEFINE_MUTEX()
API DEFINE_MUTEX() is defined in Linux and might
not be available in other OSs.
Hence remove its usage from nvgpu

Declare and explicitly initialize below mutexes
for both nvgpu and vgpu
g->mm.priv_lock
g->mm.tlb_lock

Jira NVGPU-13

Change-Id: If72885a6da0227a1552303206172f1f2b751471d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1298042
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2017-02-22 04:15:08 -08:00
Deepak Nibade
8ee3aa4b31 gpu: nvgpu: use common nvgpu mutex/spinlock APIs
Instead of using Linux APIs for mutex and spinlocks
directly, use new APIs defined in <nvgpu/lock.h>

Replace Linux specific mutex/spinlock declaration,
init, lock, unlock APIs with new APIs
e.g
struct mutex is replaced by struct nvgpu_mutex and
mutex_lock() is replaced by nvgpu_mutex_acquire()

And also include <nvgpu/lock.h> instead of including
<linux/mutex.h> and <linux/spinlock.h>

Add explicit nvgpu/lock.h includes to below
files to fix complilation failures.
gk20a/platform_gk20a.h
include/nvgpu/allocator.h

Jira NVGPU-13

Change-Id: I81a05d21ecdbd90c2076a9f0aefd0e40b215bd33
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1293187
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2017-02-22 04:15:02 -08:00
Deepak Nibade
76611c4268 gpu: nvgpu: remove use of mutex_is_locked()
mutex_is_locked() API is defined on Linux only
and not on other OS like QNX.

Hence remove use of this API for OS abstraction
support to nvgpu.

Instead of using mutex_is_locked(), use
mutex_trylock() for same purpose

Jira NVGPU-13

Change-Id: I542daf20a2294153da8e8bfe89e0dc0387297523
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1297184
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2017-02-22 04:14:57 -08:00
Alex Waterman
e99a3dec3a gpu: nvgpu: Disable IRQs only if enabled
In the PCI init/de-init code only disable IRQs if they were enabled.
The enable happens in the common power_on code. The PCI routines could
both be called without the common power_on code being called which
causes an extra disable to happen.

Bug 200275531

Change-Id: I43a8a9881f1e9ae254bf36230f29849df074657f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1301701
(cherry picked from commit cca70e9adccee1ef65a0a6d95a4494fc87500c17)
Reviewed-on: http://git-master/r/1298954
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2017-02-21 20:42:49 -08:00
Konsta Holtta
00ba4c0b0b gpu: nvgpu: assign ce_ctx->vm during ctx creation
Commit 7e403974d3 ("gpu: nvgpu: Simplify
ref-counting on VMs") accidentally broke the CE context creation while
moving away from direct ch->vm assignments. ce_ctx->vm isn't part of
that simplification, so initialize it because it's used elsewhere and
were left NULL.

Bug 1846718

Change-Id: I6219880227b881d2175005b7eaf6e6e08a6f888e
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1306221
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
2017-02-21 11:13:42 -08:00
Terje Bergstrom
c218fefe84 gpu: nvgpu: Fix unicast register accesses for SM
In two places we used broadcast register as base, but added the
unicast offset to it. This causes the write to go well beyond
valid register range.

Change the broadcast base to use unicast base instead in sequence
to resume a single SM and to record error state of SM.

Bug 200256272

Change-Id: I4ca9af2bb5877dba20ab96575f5094d42949c9e2
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
(cherry-picked from commit 04177b3414535ce5092c8baeae29883bada9d36c)
Reviewed-on: http://git-master/r/1306331
Reviewed-by: Automatic_Commit_Validation_User
2017-02-17 15:30:58 -08:00