Commit Graph

9 Commits

Author SHA1 Message Date
Peter Boonstoppel
907adfd785 gpu: nvgpu: Add NVGPU_IOCTL_CHANNEL_SET_BOOSTED_CTX
This ioctl can be used on gp10b to set a flag in the context header
indicating this context should be run at elevated clock
frequency. FECS ctxsw ucode will read this flag as part of the context
switch and will request higher GPU clock frequencies from BPMP for the
duration of the context execution.

Bug 1819874

Change-Id: I84bf580923d95585095716d49cea24e58c9440ed
Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-on: http://git-master/r/1292746
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-02-14 14:54:46 -08:00
David Nieto
6343e96f37 gpu: nvgpu: Disable ECC sysfs in GP106
The current wiring causes an attempt to re-create the
stats on dGPU re-bind

bug 1816516

Change-Id: Idb9aea08c9f80325f6ce860b2e0e482e42e973f8
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1291822
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-01-26 07:18:15 -08:00
Alex Waterman
78ad8a23ea gpu: nvgpu: Move gp106 HW headers
Move the gp106 HW headers to a new directory specially for them:

  include/nvgpu/hw/gp106

And change the code to include like so:

  #include <nvgpu/hw/gp106/hw_fb_gp106.h>

This is part of the process to restructure the nvgpu driver.

Bug 1799159

Change-Id: I76a4ff2e92021150ce65a8843bc12bb614a0e68a
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1280327
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-01-11 12:44:15 -08:00
Terje Bergstrom
ea5a214722 gpu: nvgpu: Implement SET_RD_COALESCE
Implement SW method SET_RD_COALESCE to implement correct handling
of texture read coalescing.

Bug 200223870

Change-Id: Icd6f987b72d78e5add4076fc550e2070eba70628
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1271303
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
2017-01-05 09:13:30 -08:00
Sami Kiminki
190e97f89b gpu: nvgpu: gp106: Add NVC097_SET_GO_IDLE_TIMEOUT SW method
Add the NVC097_SET_GO_IDLE_TIMEOUT SW method for GP106. This
enables booting the X server.

Bug 1732372
Bug 1792002

Change-Id: I73abaaea240039dc91c66e3862ec01a342db2fa9
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: http://git-master/r/1200637
(cherry picked from commit 0d24a6f3d8e421ea5205279166c6dc2d0f15c6a0)
Reviewed-on: http://git-master/r/1223101
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-12-27 15:26:49 +05:30
Lakshmanan M
cae5d380d8 gpu: nvgpu: Add preemption mode support for gp10x
Added preemption mode (WFI, GFXP, CTA and CILP) support for gp10x
family gr class (PASCAL_B and PASCAL_COMPUTE_B).

Bug 200221149

Change-Id: Ia8b781c5baedba660db5997f190a0b363286ed7f
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1193209
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2016-12-27 15:26:18 +05:30
Terje Bergstrom
b583ef7296 gpu: nvgpu: Disable init_preemption_state on dGPU
Discrete GPU does not have clocks wired correctly. They're needed to
be able to calculate correct preemption timeout, so disable setting
the timeout.

Change-Id: I14a6d262f6b004d40432a4e026c5558303aa90a4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1176904
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Tested-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2016-12-27 15:26:18 +05:30
Lakshmanan M
454cb1631b gpu: nvgpu: Add new CE class for gp10x
Added new CE class(PASCAL_DMA_COPY_B) for gp106 and gp104.

JIRA DNVGPU-25

Change-Id: I3c85e3ffdedf7594d41bf5c2fbebbf44addd1720
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1166709
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-12-27 15:26:17 +05:30
Terje Bergstrom
3d0f9a7517 gpu: nvgpu: Add support for gp104 and gp106
Add support for chips gp104 and gp106.

Change-Id: Ied5f239bdd0ec85245bce1fb6ef51330871d0f05
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1120465
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ken Adams <kadams@nvidia.com>
2016-12-27 15:26:16 +05:30