2 Commits

Author	SHA1	Message	Date
Sagar Kamble	3030707936	gpu: nvgpu: init auto objects for MISRA 9.1 ... Address MISRA Rule 9.1 violation: The value of an object with automatic storage duration shall not be read before it has been set. JIRA NVGPU-881 Change-Id: I63fde303b0a3e05f16b9ce518684a37c774f0f43 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1929824 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2018-10-23 15:44:50 -07:00
Mahantesh Kumbar	07cb84214b	gpu: nvgpu: SEC2 IPC support ... -Created sec2_ipc.c to support SEC2 IPC. -Defined nvgpu_sec2_cmd_post() to send command to SEC2 RTOS from nvgpu along with dependent methods like seq acquire/release, validate & write cmd. -Defined nvgpu_sec2_process_message() to process message from SEC2 RTOS & route to correct handler based on flag. -Method sec2_process_init_msg() helps fetch parameters sent from SEC2 RTOS to setup queue, debug buffer as parameters. -Created sec2 ops under gops to access sec2 engine specific HALs. -Defined nvgpu_sec2_queue_init() init command & message for SEC2 RTOS using common falcon queue. -Made Makefile changes to include sec2_ipc.c for build JIRA NVGPUT-82 Change-Id: I6e4c2d6ec71aa61a543f34680d1412167c9a8cc6 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1828034 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2018-10-12 17:35:08 +05:30