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1329 Commits

Author SHA1 Message Date
Sagar Kamble
53dc53a8b4 gpu: nvgpu: add hal to get the bar2 vm size 
On ga10b+ platforms, more VM space is needed to map various buffers
to bar2 vm. Engine method buffer is mapped for each pbdma and for
maximum supported TSGs this requires more than 32MB of space.
Also we need to consider fault buffer space and vab buffer
space requirement.

Bug 3958581

Change-Id: I9ee87119f762352ee12859b71c08a5f75b3554e0
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2872811
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-03-25 02:45:47 -07:00
Santosh BS
2a865e3aad gpu: nvgpu: NVENC support on TU104 
This patch adds nvenc support for TU104
- Fetch engine/dev info for nvenc
- Falcon NS boot (fw loading) support
- Engine context creation for nvenc
- Skip golden image for multimedia engines
- Avoid subctx for nvenc as it is a non-VEID engine
- Job submission/flow changes for nvenc
- Code refactoring to scale up the support for other multimedia
  engines in future.

Bug 3763551

Change-Id: I03d4e731ebcef456bcc5ce157f3aa39883270dc0
Signed-off-by: Santosh BS <santoshb@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2859416
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-24 17:07:49 -07:00
vivekku
d5e00ef380 gpu: nvgpu: hal: enable gsp scheduler 
- enable gsp scheduler for orin silicon platforms
- disabled gsp scheduler for simulation and enabled KMD scheduler

Bug 3935433

Change-Id: I38cb35937ffb25b76fbf37fa4eeb9e993f0370c5
Signed-off-by: vivekku <vivekku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2872897
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Prateek Sethi <prsethi@nvidia.com>
Reviewed-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-21 02:38:01 -07:00
Richard Zhao
f791adf880 gpu: nvgpu: move .runlist.hw_submit to use runlist_id 
Use detailed function parameters runlist_id, iova/aperture and count, so
the HAL could be reused on server side.

Jira GVSCI-15773

Change-Id: I28f68682b9eea4e798af5c850c87840bd9b79970
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863444
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-21 02:31:29 -07:00
Richard Zhao
da1da8f563 gpu: nvgpu: move .preempt_trigger/.is_preempt_pending to IDs 
.preempt_tsg uses .preempt_trigger/.is_preempt_pending, so they both
have to use runlist_id and tsgid too.

Jira GVSCI-15770

Change-Id: Ida24d160c362ea1348d7c19e6d0352bb390d0a64
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863442
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-21 02:30:57 -07:00
Richard Zhao
8f5adab299 gpu: nvgpu: .preempt_tsg move to use runlist_id/tsgid 
It's for making .preempt_tsg reusable on server side.

Jira GVSCI-15770

Change-Id: Id9f477baa29cb63fb0e1d1650f4b1e6a2fa248c0
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863441
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-21 02:30:49 -07:00
Richard Zhao
41823694a3 gpu: nvgpu: add .init_golden_image HAL 
golden image is created differently on native and VF.

Jira GVSCI-15772

Change-Id: I8d78d1214d8aac1d39d6529b68adef1dd6f8a516
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863440
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-03-17 04:04:33 -07:00
atanand
9dd2a8fc73 gpu: nvgpu: Get GA10B EMC floorsweeping status 
The memory bandwidth reported by the nvgpu driver is a resultant of FBP and EMC floorsweeping status. The FBP floorsweep status was already getting reported in the GPU characterstics so the status of EMC was fetched and reported in this change.

Jira NVGPU-9609
Bug 3661074

Change-Id: Ia2fe6cb029d086765da15d9e964ea77256e06604
Signed-off-by: atanand <atanand@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2859237
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-03-17 04:00:00 -07:00
vivekku
eb52414f22 gpu: nvgpu: ga10b: disable gsp scheduler 
Changes:
- disabling gsp scheduler

Bug 3935433

Change-Id: Iedb049b0ad1f052e8b3d1692d9280e80dcee9163
Signed-off-by: vivekku <vivekku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2869839
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-03-17 03:56:24 -07:00
prsethi
6b2c080f8f gpu:nvgpu: add enable flag for KMD_SCHEDULING_WORKER_THREAD support 
Currently KMD_SCHEDULING_WORKER_THREAD can be enabled/disabled using
compile time flag but this flag does give ability to control the
feature based on the chip.
GSP is enabled only on ga10b where KMD_SCHEDULING_WORKER_THREAD should
be disabled while should be enabled for other chips at the same time
to support GVS tests.
Change adds enabled flag to control KMD_SCHEDULING_WORKER_THREAD based
on the chip.

Bug 3935433

Change-Id: I9d2f34cf172d22472bdc4614073d1fb88ea204d7
Signed-off-by: prsethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2867023
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-03-17 03:55:02 -07:00
Richard Zhao
84ddb23633 gpu: nvgpu: move .force_ctx_reload to use runlist_id and chid 
Moving to use IDs rather than struct makes it reusable on server side.

Jira GVSCI-15770

Change-Id: Id4e815e9cf78a43156449d0e77e8e331fc906725
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863439
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-13 04:56:10 -07:00
Richard Zhao
c8d6a91de6 gpu: nvgpu: update .channel.enable/disable to use runlist_id and chid 
Moving to use IDs rather than struct makes it reusable on server side.

Jira GVSCI-15770

Change-Id: Ibd94ab8c9f0492bd6d20243525905d637eb8de66
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863438
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-13 04:56:04 -07:00
Richard Zhao
d9c8d317f0 gpu: nvgpu: update .read_state to use runlist_id and chid 
Moving to use IDs rather than struct makes it reusable on server side.

Jira GVSCI-15770

Change-Id: Ia5e30ebb0e8092b9cdc4c3f3cd524f585fd4b410
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863437
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-13 04:55:58 -07:00
Richard Zhao
2ff110f722 gpu: nvgpu: update .clear to use runlist_id and chid 
- Moving to use IDs rather than struct makes it reusable on server side.
- move channel bind/unbind to use .enable/.clear HALs

Jira GVSCI-15770

Change-Id: I86d4aae2953024e537e32a35fe9cabb1b91cd201
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863436
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-13 04:55:53 -07:00
Richard Zhao
a7d358f773 gpu: nvgpu: vf: init gmmu related structure 
vf driver implements gmmu map/unmap on client side.

- adds helper function to check whether nvgpu device is vf or legacy
vgpu.
- inits pd_cache struct for vf
- inits platform->phys_addr for ipa2pa

Jira GVSCI-15733

Change-Id: I46c84f0acdd167b9c4bdcec2f1c25f3acd6a0f71
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863430
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Prathap Kumar Valsan <prathapk@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-12 08:13:47 -07:00
Richard Zhao
de0e1be1ed gpu: nvgpu: add g->func_regs 
rework nvgpu_func_* io accessors to use g->func_regs rather than use
g->regs. g->regs is invalid for VF.

Jira GVSCI-15732

Change-Id: I71e788ff135c5a286b273c151e1bd0a88e9d61e2
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863429
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-12 08:13:41 -07:00
Kishan
a765a76c81 gpu:nvgpu: Expose physical gpc,tpc layout for ecc sysfs nodes. 
Added new gr_config member to hold TPC physical id map.
Updated ecc stats structures to hold physical gpc,tpc
numbers. Previously logical id's were exposed via ecc
sysfs nodes.
Consumers of ecc sysfs nodes refer tpc_fs_mask which is
physical gpc/tpc layout whereas ecc sysfs nodes were updated
with logical gpc/tpc layout. This change ensures that both
use the same framework.

JIRA NVGPU-9607
Bug 3950378

Change-Id: I1f91956dd027ffdc12042dd33dc491a3ce1e1ff6
Signed-off-by: Kishan <kpalankar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2866264
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-08 06:32:00 -08:00
Sagar Kamble
2acfb55780 gpu: nvgpu: fix tex rd coalesce disable logic 
NETLIST_REGIONID_SW_CTX_LOAD writes update gr_gpcs_tpcs_tex_m_dbg2_r to
default value that keeps rd coalesce enabled for LG & SU.

Disable rd coalesce for tex, lg and su after NETLIST_REGIONID_SW_CTX_LOAD
writes during gr init and golden ctx init for it to take effect.

For gr sw method handling, don't update the tex rd coalesce on interrupt
with offset *_SET_RD_COALESCE as we want to keep rd coalescing disabled.

Bug 3881919

Change-Id: Ie7e6616d48f84547ce3380bfa395910b7995c05b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2857141
(cherry picked from commit b2c8827c65)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2859538
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-07 22:46:44 -08:00
V M S Seeta Rama Raju Mudundi
ab46ee3335 Revert "gpu:nvgpu: Expose physical gpc,tpc layout for ecc sysfs nodes." 
This reverts commit 2cc098eae7.

Reason for revert: intermittent boot failures on drv-orin-f1 and 
frspr-f1 on both AV+L and AV+Q.

Bug 3998230

Change-Id: I230ba7ba469fde3f470dab7538cc757c99360d99
Signed-off-by: srajum <srajum@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863208
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-02-25 11:16:12 -08:00
Kishan
2cc098eae7 gpu:nvgpu: Expose physical gpc,tpc layout for ecc sysfs nodes. 
Added new gr_config member to hold TPC physical id map.
Updated ecc stats structures to hold physical gpc,tpc
numbers. Previously logical id's were exposed via ecc
sysfs nodes.
Consumers of ecc sysfs nodes refer tpc_fs_mask which is
physical gpc/tpc layout whereas ecc sysfs nodes were updated
with logical gpc/tpc layout. This change ensures that both
use the same framework.

JIRA NVGPU-9607
Bug 3950378

Change-Id: Iac99951fc3aa9dde02e833109f32aa5bb37ea15f
Signed-off-by: Kishan <kpalankar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2855032
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-02-22 00:42:23 -08:00
Rajesh Devaraj
b754a2f0cf gpu: nvgpu: add and update falcon_dump_stats 
Add dump_falcon_info to avoid the duplication of entire
falcon_dump_stats function for new chips.

JIRA NVGPU-9216

Change-Id: I0a0c7b4655c625222a8fd3538d9e855568616e3a
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2858843
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-02-18 14:07:09 -08:00
Rajesh Devaraj
4bbc766454 gpu: nvgpu: add intr_0_pbcrc_pending gops for pbdma 
Add intr_0_pbcrc_pending hal to avoid duplication of the entire function
for new chips.

JIRA NVGPU-9325

Change-Id: Ia08ce7761ac5b9a1af1166efbc1ecba97b54fc87
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2857919
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-02-17 07:31:23 -08:00
Rajesh Devaraj
5aae7df6cd gpu: nvgpu: add reset_method pbdma gops 
Add reset_method hal to avoid duplication of the entire function
for new chips.

JIRA NVGPU-9325

Change-Id: Ice9c3f6aea33a8dadae5841f1a6387303495ba98
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2854547
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-02-17 07:26:24 -08:00
Rajesh Devaraj
2e73de831f gpu: nvgpu: add is_sw_method_subch pbdma gops 
Add is_sw_method_subch hal to avoid duplication of the entire function
for new chips.

JIRA NVGPU-9325

Change-Id: If18a2d510f77e269cb00dde609ec1c5941622858
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2855046
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Prathap Kumar Valsan <prathapk@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-02-13 05:40:54 -08:00
Rajesh Devaraj
73679f1ec8 gpu: nvgpu: update enable_fifo_interrupts 
To reuse enable_fifo_interrupts API in future chips, this patch renames
it as ga10b_fifo_enable_intr and adds it to FIFO specific header file.

JIRA NVGPU-9325

Change-Id: I9f313e417281d5861f568bd41593c5135d9c77a9
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2848816
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-01-31 04:19:57 -08:00
Rajesh Devaraj
77841cc9bb gpu: nvgpu: update pbdma_acquire intr handling 
To reduce duplication of pbdma_handle_intr_0_legacy to new chips, this
patch makes handle_intr_0_acquire as a HAL.

JIRA NVGPU-9325

Change-Id: I225318d45078367d09fc114202d9aeb0f1be374b
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2844872
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-01-24 03:38:01 -08:00
Austin Tajiri
6fffdddb7a gpu: nvgpu: add priv_ring.intr_retrigger HAL 
Add a priv_ring.intr_retrigger HAL for chips that need to
retrigger pending interrupts in the PRIV_RING ISR.

Jira NVGPU-9217

Change-Id: I976f26a39d148a0ce1ad54b53d982dc0af58197b
Signed-off-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2839756
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-01-23 22:51:54 -08:00
Rajesh Devaraj
4bb32e33e7 gpu: nvgpu: update pbdma_dump_intr_0 as an hal 
To reduce the duplication of HALs to new chips, this makes pbdma
dump_intr_0 as an HAL.

JIRA NVGPU-9325
JIRA NVGPU-9064

Change-Id: I737146068cb144165bae8666c04f876aed20a89c
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2847566
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-01-23 22:39:36 -08:00
Rajesh Devaraj
afb971b66e gpu: nvgpu: update report_pbdma_error as hal 
To reduce the duplication pbdma_handle_intr_0 API to new chips, this
patch converts report_pbdma_error as a HAL.

JIRA NVGPU-9325

Change-Id: Ifcb0838037c750070c26343e008a176b26eebf16
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2845088
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-01-20 03:40:17 -08:00
Richard Zhao
4ed84db8a5 gpu: nvgpu: vgpu: add vgpu-next support for hal init 
vgpu-next is enabled only for internal build.

Jira GVSCI-15646

Change-Id: I5a829a91da2ca0f4f4d445f5337be8983baab36d
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2840221
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Aparna Das <aparnad@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-01-12 23:01:06 -08:00
Rajesh Devaraj
3e2eff564f gpu: nvgpu: update pbdma intr enable set/clear masks as hals 
To reduce the entire duplication of pbdma_intr_enable for future chips,
make set and clear masks as HALs.

JIRA NVGPU-9325

Change-Id: Id8434fc15ca4bf542680a8452dc294f2c4068084
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2838036
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-01-09 20:04:11 -08:00
Rajesh Devaraj
b9e771ecfc gpu: nvgpu: split capture_ram_dump api 
This patch splits capture_ram_dump into two parts to separate out
NV_RAMFC_TOP_LEVEL_GET/NV_RAMFC_TOP_LEVEL_GET_HI into a new api. This
split helps in reducing duplication of capture_ram_dump in future chips.

JIRA NVGPU-9325

Change-Id: I4dba2db7c08406af1569e28037b2aa2f2abfc782
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2836197
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-01-05 05:45:15 -08:00
Ramalingam C
1dc067c86b gpu: nvgpu: Reuse warp_esr_error functions 
Mark gr_gv11b_handle_warp_esr_error_mmu_nack and
gr_gv11b_handle_all_warp_esr_errors as extern for reusage in
upcoming chips

JIRA NVGPU-9073

Change-Id: Id443ff457628835cc0fde819eb68cbdcabce144e
Signed-off-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2821787
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-01-04 06:50:08 -08:00
Rajesh Devaraj
2d3745810b gpu: nvgpu: add support flag for gsp stress test 
Add support flag for GSP stress test.

JIRA NVGPU-9347

Change-Id: I6b93e085b4e25798f1227297fd1baba8c1380604
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2833485
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-01-03 19:09:17 -08:00
Ramalingam C
2c8cfde803 gpu: nvgpu: use hals for perfmon_regs_base 
Use hals for the perfmon_regs_base at
	gr_gv11b_pri_pmmgpcrouter_addr
	gr_gv11b_pri_pmmfbprouter_addr

This helps to reduce the code duplications for upcoming chips

JIRA NVGPU-9073

Change-Id: I36ded2cb618249df555181cceeb81c524c78d587
Signed-off-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2828585
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-12-21 22:24:57 -08:00
Ramalingam C
4c22d5c35d gpu: nvgpu: Add hals for router_perfmon_regs_base 
gv11b onwards add hals
        get_hwpm_gpcrouter_perfmon_regs_base
        get_hwpm_fbprouter_perfmon_regs_base

And remove the ga10b version of same as that is redundant.

This is preparatory patch to update the gr_gv11b_pri_pmmgpcrouter_addr
and gr_gv11b_pri_pmmfbprouter_addr with the hals

JIRA NVGPU-9073

Change-Id: I8b04f9b61784ca2c09b248655435ea7a7ab92926
Signed-off-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2828584
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-12-21 22:24:45 -08:00
vivekku
470c1738b5 gpu: nvgpu: gsp: host routed interrupt handling 
Changes:
- support for watchdog timer interrupt handling
- code modified to support gsp scheduler interrupts for ecc errors
directed to host
- interrupts like IMEM, DMEM, EMEM, Delayed Lock Step and incorrect
Register access

NVGPU-9273

Change-Id: I93a2ef0961aaa40e76ca7efe8450ce07a6709453
Signed-off-by: vivekku <vivekku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2818202
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
Tested-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-12-21 11:59:25 -08:00
Ramalingam C
f5f13778ad gpu: nvgpu: Use hals for getting strides 
Get the gpc stride and ppc in gpc stride from get_litter_value hal.

JIRA: NVGPU-9073

Change-Id: Id7cea2dacd8210836ce016e6f84d5c34eac267d8
Signed-off-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2831031
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-12-21 06:32:14 -08:00
rmylavarapu
81ba21f031 gpu: nvgpu: enable gsp scheduler on embedded linux profile 
Currently the gsp scheudler is enabled for all linux configurations and
this change will enable the gsp scheduler on embedded linux profile and
will disable on l4t.
One of the gsp ga10b hal funcion is used by nvgpu-next so the defination
is moved out of gsp scheduler flag

NVGPU-9297

Change-Id: If457db46e26d8f5be01f643c75a22aafb86bd7f3
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2826152
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-12-17 11:44:36 -08:00
Tejal Kudav
ee81e3ee34 nvgpu: Disable gsp func ISR when mon is present 
On QNX safety builds, when Mon is present, SWGEN0 intr will be handled
as part of devctl DCMD_NOTIFY_GSP_INTR.

JIRA NVGPU-7442

Change-Id: Ibe3526526821c81c9abaadf74f3d35da9708bfb3
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2826149
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-12-17 06:26:13 -08:00
Seeta Rama Raju
e0a9553533 gpu: nvgpu: Add magic value at instance block 
This is adding magic value in instance block while
initializing instance block for a context. This will
be verified by FECS firmware.

Bug 3638810

Change-Id: I7d304c1b622b3c9f50a7443e9fadce9bac869258
Signed-off-by: Seeta Rama Raju <srajum@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2786274
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-12-17 02:21:07 -08:00
mpoojary
9b73378362 gpu: nvgpu: Add support for loading ctxsw encrypted binaries 
Add checks to load encrypted CTXSW binaries for T234,
when executing in silicon; else load the non encrypted
binaries.

Jira NVGPU-9303

Change-Id: Icf55ed76b1a7340006b00d1c24472d26462a880c
Signed-off-by: mpoojary <mpoojary@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2819642
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Dinesh Kamalakannan <dineshka@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
 2022-12-14 23:48:10 -08:00
rmylavarapu
01eb416745 gpu: nvgpu: gsp sched: enable gsp sw init for safety build 
Changes
1. Remove dGPU flag dependency on calling gsp sw init on tot.
2. Created Enable flag for gsp scheduler to enable them on ga10b
platforms.
3. Engine config flag is only enabled for dGPU enabled platforms, as gsp
is using engine functions it need to be enabled for all gsp sched
enabled builds.
4. Changes in gsp_sequence_init/de_init where on qnx we are seeing
issues.

NVGPU-9297

Change-Id: Ia4bce85ae8fd2794da1553e9ea418c76845a10ac
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2822537
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-12-12 06:06:09 -08:00
rmylavarapu
398a30a546 gpu: nvgpu: gsp sched: get the binary file names as per debug fuse 
Changes
 1. Created gsp hal function to read the hardware config register
    to tell whether the board is debug fused.
 2. Created function to get the binary file names as per debug fuse.

NVGPU-9295
Bug 3897331

Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Change-Id: Ia8462aa6f3d8d0d538c06f35245c965e106b3d37
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2822443
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-12-11 19:09:29 -08:00
Dinesh T
373398a46b gpu: nvgpu: Add os specific call to initialize the channels 
Add OS specific function to return the number of syncpoints
available to the GPU. This is required for making the
syncpoints as configurable.

Linux: The default number of syncpoints is 512.

Bug 3644504

Change-Id: Iddbc38cb25480876d6d8f39f039218a1b2b22605
Signed-off-by: Dinesh T <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2820152
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-12-06 04:47:24 -08:00
Ramalingam C
093974e397 gpu: nvgpu: ga10b: use a hal instead of a macro 
Use the g->ops.grmgr.get_allowed_swizzid_size() hal instead of
smcarb_allowed_swizzid__size1_v(). This helps to avoid the duplication
of another hal when the macro changes for new chips.

JIRA: NVGPU-9078

Change-Id: I2dfb927172c30e945c2c20da7dd64f7f17bc71ae
Signed-off-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2814618
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-11-30 10:43:16 -08:00
Debarshi Dutta
5d2dfc88a3 gpu: nvgpu: Replace CONFIG_NVS_KMD_BACKEND 
Use CONFIG_KMD_SCHEDULING_WORKER_THREAD instead of
CONFIG_NVS_KMD_BACKEND to remove confusion about the CPU based
KMD scheduling worker thread.

The KMD based scheduling worker thread caters to both Manual Mode
CPU based scheduler as well as Automatic Round Robin CPU based
scheduler.

For the traditional submit path, add correct handling of the
CONFIG_NVS_PRESENT. CPU based worker thread should be part of
CONFIG_NVS_PRESENT. Eventually, when DCONFIG_KMD_SCHEDULING_WORKER_THREAD
is removed, the application must switch to GSP.

Jira NVGPU-8619

Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Change-Id: I0886ef3b2e0124b6fe22c2bf0bf7d1fa98039d00
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2810217
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-11-23 08:07:24 -08:00
vivekku
a687c78077 gpu: nvgpu: exit PMU functions if PMU state is OFF 
Add a condition to exit PMU functions if PMU FW state is
Set to OFF as these functions could be called from main
GPU thread or pg task thread but PMU sub-unit is exited
as part of power off sequence.

Bug 3812500

Change-Id: I8e8de411e1cb2b0ffe1991814ce8209113490272
Signed-off-by: vivekku <vivekku@nvidia.com>
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2789329
(cherry picked from commit 71253495bf994c1e17ea18146451b50e4e64bba5)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2789518
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Tested-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-11-22 21:56:51 -08:00
Rajesh Devaraj
69adc6c91d gpu: nvgpu: add null check for mssnvlink hals 
Add NULL check for mssnvlink related HALs.

JIRA NVGPU-9263

Change-Id: I418191c11aabdb614255220d4e26120e9301a2d2
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2806101
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-11-17 11:26:58 -08:00
Sagar Kamble
d1b28712b6 gpu: nvgpu: implement VEID alloc/free 
Implement the ioctls NVGPU_TSG_IOCTL_CREATE_SUBCONTEXT and
NVGPU_TSG_IOCTL_DELETE_SUBCONTEXT. These will allocate and
free the VEID numbers.

Address space association with the VEIDs is verified to
ensure that channels association with VEIDs and address
space remains consistent.

Bug 3677982
JIRA NVGPU-8681

Change-Id: I2d913baf61a6bdeec412c58270c0024b80ca15c6
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2766765
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-11-01 00:05:18 -07:00