Commit Graph

219 Commits

Author SHA1 Message Date
Terje Bergstrom
f9fd5bbabe gpu: nvgpu: Unify PDE & PTE structs
Introduce a new struct gk20a_mm_entry. Allocate and store PDE and PTE
arrays using the same structure. Always pass pointer to this struct
when possible between functions in memory code.

Change-Id: Ia4a2a6abdac9ab7ba522dafbf73fc3a3d5355c5f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/696414
2015-04-04 18:07:35 -07:00
Terje Bergstrom
a3b26f25a2 gpu: nvgpu: TLB invalidate after map/unmap
Always invalidate TLB after mapping or unmapping, and remove the
delayed TLB invalidate.

Change-Id: I6df3c5c1fcca59f0f9e3f911168cb2f913c42815
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/696413
Reviewed-by: Automatic_Commit_Validation_User
2015-04-04 18:06:37 -07:00
Amit Sharma (SW-TEGRA)
80d26baf05 gpu: nvgpu: Fix NULL instead of interger
Fixed the following sparse warning using proper NULL instead of '0':
- mm_gk20a.c:1301: warning: Using plain integer as NULL pointer

Bug 200067946

Change-Id: Idd84f541711682bf097bb474049d523a5bb01ae2
Signed-off-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com>
Reviewed-on: http://git-master/r/682242
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
2015-04-04 18:06:34 -07:00
Terje Bergstrom
24ddf71b90 gpu: nvgpu: Use busy looping on memory ops
Use busy looping on L2 and TLB maintenance operations. This speeds
them up by an order of magnitude.

Add also trace points to measure performance for memory ops and
interrupt processing.

Change-Id: Ic4a8525d3d946b2b8f57b4b8ddcfc61605619399
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/681640
2015-04-04 18:05:22 -07:00
Konsta Holtta
5b6e8995b2 gpu: nvgpu: use vm param to vm_map/unmap_buffer
Pass vm instead of as share to the userspace buffer mapping functions,
since they need to be called also from other places than just the AS
device ioctls, and as share is specific to them.

Bug 1573150

Change-Id: I994872f23ea7b1582361f3f4fabbd64b4786419c
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/674020
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-04-04 18:04:48 -07:00
Konsta Holtta
8991080a99 gpu: nvgpu: use gk20a_free_inst_block in remove_vm
Use the common instance block freeing function when removing vm.

Change-Id: I1dfaaceb57e01d0a1359ce5742ed55d81dff10ed
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/672033
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-04-04 18:04:48 -07:00
Terje Bergstrom
4aef10c950 gpu: nvgpu: Set compression page per SoC
Compression page size varies depending on architecture. Make it
129kB on gk20a and gm20b.

Also export some common functions from gm20b.

Bug 1592495

Change-Id: Ifb1c5b15d25fa961dab097021080055fc385fecd
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/673790
2015-04-04 18:04:45 -07:00
Seshendra Gadagottu
f4883ab97a gpu:nvgpu: add bar2 aperture support
Bug 1587825

Change-Id: I884c6b268aabb04b4990713395ebedf92410e02a
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/659239
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-04-04 18:04:38 -07:00
Konsta Holtta
2dda8077ec gpu: nvgpu: unify instance block initialization
Create gk20a_init_inst_block() to reduce reg write clutter when
initializing instance blocks, which is done in several places.

Change-Id: Idcb8b604851a849e0bb6abce5743c9f4cbf98033
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/672434
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-04-04 18:04:35 -07:00
Alex Waterman
4f693d032a gpu: nvgpu: Change va_node free behavior
Decrement the ref count on all mapped_buffers belonging to a va_node
when a va_node is freed. This prevents userspace from leaking some
mapped_buffers in some cases.

This does prevent userspace from keeping a buffer around after freeing
a space allocation if the buffer in question is not otherwise ref
counted. Not sure if this is a bad thing for userspace or not.

Bug 1600686

Change-Id: I659ccbda5935d44086fd367bd2110f7d0f066194
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/676629
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-04-04 18:04:19 -07:00
Terje Bergstrom
f11443daff gpu: nvgpu: Add SMMU bit only if SMMU enabled
If SMMU is disabled, we should not add the SMMU bit to addresses.

Change-Id: I6dd82e18b63474fb487d21f421ef06467551595b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/673250
Reviewed-by: Adeel Raza <araza@nvidia.com>
Tested-by: Adeel Raza <araza@nvidia.com>
2015-04-04 18:03:22 -07:00
Alex Waterman
a99bbc5f60 gpu: nvgpu: make larger address space work
Implement several fixes for allowing the GVA address space to grow
to larger than 32GB and increase the address space to 128GB.

 o  Implement dynamic allocation of PDE backing pages. The memory
    to store the PDE entries was hard coded to 1 page. Now the
    number of pages necessary is computed dynamically based on the
    size of the address space and the size of large pages.

 o  Fix an arithmetic problem in the gm20b sparse texture code
    that caused large address spaces to be truncated when sparse
    PDEs/PTEs were being filled in. This caused a kernel panic
    when freeing the address space since a lot of the backing
    PTE memory was not allocated.

 o  Change the address space split for large and small pages. Small
    pages now occupy the bottom 16GB of the address space. Large
    pages are used for the rest of the address space. Now, with a
    128GB address space, there are 112GB of large page GVA available.

This patch exists to allow large (16GB) sparse textures to be allocated
without running into lack of memory issues and kernel panics.

Bug 1574267

Change-Id: I7c59ee54bd573dfc53b58c346156df37a85dfc22
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/671204
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-04-04 18:02:38 -07:00
Konsta Holtta
4ccb162da7 gpu: nvgpu: unify instance block creation
Reduce copypaste code in instance block allocation and deletion with
functions purposed for that.

Change-Id: I2c8ae6a317ac89e2c857dde4296cb4316b8aaafe
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/668698
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-04-04 15:06:38 -07:00
Konsta Holtta
a9423dd192 gpu: nvgpu: fix list_add_tail in dmabuf state
Fix a memory leak: add the newly created state to the dmabuf priv's
state list, instead of the other way around.

Bug 1594784
Bug 200064154

Change-Id: I939746a254bb8bf4d06de7fcecba06c191da665f
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/668758
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Lauri Peltonen <lpeltonen@nvidia.com>
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
2015-04-04 15:06:03 -07:00
Dan Willemsen
b53b2973fe gpu: nvgpu: Fix/HACK for v3.18
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
2015-03-18 20:19:10 -07:00
Terje Bergstrom
0bc513fc46 gpu: nvgpu: Remove gk20a sparse texture & PTE freeing
Remove support for gk20a sparse textures. We're using implementation
from user space, so gk20a code is never invoked.

Also removes ref_cnt for PTEs, so we never free PTEs when unmapping
pages, but only at VM delete time.

Change-Id: I04d7d43d9bff23ee46fd0570ad189faece35dd14
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/663294
2015-03-18 12:12:32 -07:00
Terje Bergstrom
5477d0f4c2 gpu: nvgpu: Generic mem_desc & allocation
Make mem_desc a generic container for buffers. Add functions for
allocating and mapping buffers to an address space which store their
data in mem_desc.

Change-Id: I031643442c6fd41f5e7222fe9b7bfcaf9b784db5
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/660908
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
2015-03-18 12:12:27 -07:00
Hiroshi Doyu
75af9eb590 gpu: nvgpu: detect iommu'ability dynamically
A device can be iommu'able whenever it's registered so that this patch
detects its iommu'ability dynamically.

Bug 1577389

Change-Id: I8ea20e5dd997fc1a399f517c17783323f238ecc3
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/606019
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:12:21 -07:00
Terje Bergstrom
2d71d633cf gpu: nvgpu: Physical page bits to be per chip
Retrieve number of physical page bits based on chip.

Bug 1567274

Change-Id: I5a0f6a66be37f2cf720d66b5bdb2b704cd992234
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/601700
2015-03-18 12:12:19 -07:00
Konsta Holtta
28f4e53e74 gpu: nvgpu: l2 invalidate/flush for off devices
When doing l2 invalidate or l2 flush, first check if the hw is powered
on. If it is not, nothing is done, as there are no hardware registers
available. As a side-effect, this may race so that the hardware stays
unrailgated.

Change-Id: I8bdbfcee3545355435d4ae01476188eb1b8b8817
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/594441
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:12:17 -07:00
Terje Bergstrom
1d9fba8804 gpu: nvgpu: Per-alloc alignment
Change-Id: I8b7e86afb68adf6dd33b05995d0978f42d57e7b7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/554185
GVS: Gerrit_Virtual_Submit
2015-03-18 12:12:15 -07:00
Sami Kiminki
f97e7036b1 gpu: nvgpu: sanitize gk20a_vm_alloc_share()
Add sanity check for big_page_size parameter to avoid invoking
gk20a_init_vm() with a bogus big page size, potentially hitting a
BUG_ON there. Also, reorganize the code a bit to avoid memory leak in
case of bogus big page size, and properly forward the return value
from gk20a_init_vm().

Change-Id: I4eeada75415d2e9539b5e8859099cce35cd86db3
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: http://git-master/r/594469
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:12:08 -07:00
Sami Kiminki
ca474ca33f gpu: nvgpu: ALLOC_AS: don't fail on default big page size
gk20a_vm_alloc_share() fails when the default big page size is
requested but ops.mm.set_big_page_size is unset. Rework the logic a
bit to allow userspace to explicitly request the default big page
size, too.

Change-Id: I2a28c6d979fbf1dde5559ce9eb5f1310d232e27f
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: http://git-master/r/590456
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:12:08 -07:00
Terje Bergstrom
2c5fdd1c8a gpu: nvgpu: Fix comptag calculation for 64k pages
Comptags are assigned per 128k. For 64k pages this means we need to
assign same index to two pages. Change the logic to use byte sizes.

Change-Id: If298d6b10f1c1cad8cd390f686d22db103b02d12
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/594403
2015-03-18 12:12:07 -07:00
Jussi Rasanen
529962911c gpu: nvgpu: cde: Combine H and V passes
When using CDE firmware v1, combine H and V swizzling passes into one
pushbuffer submission. This removes one GPU context switch, almost
halving the time taken for swizzling.

Map only the compbit part of the destination surface.

Bug 1546619

Change-Id: I95ed4e4c2eefd6d24a58854d31929cdb91ff556b
Signed-off-by: Jussi Rasanen <jrasanen@nvidia.com>
Reviewed-on: http://git-master/r/553234
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:12:06 -07:00
Konsta Holtta
eb74267b83 gpu: nvgpu: free all vm's when removing support
Remove both bar1 and pmu.

Bug 1476801

Change-Id: I0c194db06b576083ddaab3726b8575ebce473d84
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/592114
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:12:05 -07:00
Konsta Holtta
97e6847cb1 gpu: nvgpu: don't kfree vm's inside other structs
Trying to kfree pmu.vm or bar1.vm is not allowed, since they are not
directly allocated. Separate the vm kfree from the actual vm support
removal, so that they can be done individually.

Change-Id: I7628f546b94e0de909371ce315e4cb065e5ef953
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/592112
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:12:05 -07:00
Konsta Holtta
e4654ebb01 gpu: nvgpu: destroy big page allocator only if set
Some vm's do not have big pages.

Bug 1476801

Change-Id: Ic82ca7a1380834ea30582631af224c81fd01e4bb
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/592113
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:12:05 -07:00
Deepak Nibade
b3f575074b gpu: nvgpu: fix sparse warnings
Fix below sparse warnings :

warning: Using plain integer as NULL pointer
warning: symbol <variable/funcion> was not declared. Should it be static?
warning: Initializer entry defined twice

Also, remove dead functions

Bug 1573254

Change-Id: I29d71ecc01c841233cf6b26c9088ca8874773469
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/593363
Reviewed-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
2015-03-18 12:12:01 -07:00
Sam Payne
8c6a9fd115 Revert "gpu: nvgpu: GR and LTC HAL to use const structs"
This reverts commit 41b82e97164138f45fbdaef6ab6939d82ca9419e.

Change-Id: Iabd01fcb124e0d22cd9be62151a6552cbb27fc94
Signed-off-by: Sam Payne <spayne@nvidia.com>
Reviewed-on: http://git-master/r/592221
Tested-by: Hoang Pham <hopham@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mitch Luban <mluban@nvidia.com>
2015-03-18 12:11:56 -07:00
Terje Bergstrom
4f6dddcf78 gpu: nvgpu: Allow compression on 64k pages
Allow compression always when page size matches the big page
size for the context.

Bug 1558739

Change-Id: I27b0aed06c24d69bd1555626b9affb1149536615
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/590422
2015-03-18 12:11:55 -07:00
Terje Bergstrom
2d5ff668cb gpu: nvgpu: GR and LTC HAL to use const structs
Convert GR and LTC HALs to use const structs, and initialize them
with macros.

Bug 1567274

Change-Id: Ia3f24a5eccb27578d9cba69755f636818d11275c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/590371
2015-03-18 12:11:54 -07:00
Terje Bergstrom
fcf4a10799 gpu: nvgpu: VM size should be u64
VM size should not depend on CPU architecture. It should be always
u64.

Change-Id: I81539807f6674877fd04f0079b2bec05b2a0640d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/562466
2015-03-18 12:11:50 -07:00
Terje Bergstrom
2eb6dcb469 gpu: nvgpu: Implement 64k large page support
Implement support for 64kB large page size. Add an API to create an
address space via IOCTL so that we can accept flags, and assign one
flag for enabling 64kB large page size.

Also adds APIs to set per-context large page size. This is possible
only on Maxwell, so return error if caller tries to set large page
size on Kepler.

Default large page size is still 128kB.

Change-Id: I20b51c8f6d4a984acae8411ace3de9000c78e82f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:11:46 -07:00
Terje Bergstrom
ecc6f27fd1 gpu: nvgpu: Common VM initializer
Merge initialization code from gk20a_init_system_vm(),
gk20a_init_bar1_vm() and gk20a_vm_alloc_share() into gk20a_init_vm().

Remove redundant page size data, and move the page size fields to be
VM specific.

Bug 1558739
Bug 1560370

Change-Id: I4557d9e04d65ccb48fe1f2b116dd1bfa74cae98e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:11:46 -07:00
Sami Kiminki
0858058e50 gpu: nvgpu: Report error on failed map
gk20a_vm_map_buffer() used to ignore silently map requests for
non-dmabuf fd:s. Fix this by returning the error code from
dma_buf_get().

Bug 1566862

Change-Id: If01b03f43b67b17d9fb997d914db871520f50c6e
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
2015-03-18 12:11:46 -07:00
Konsta Holtta
026781c82c gpu: nvgpu: require mapped buffer be inside va
When validating buffers to be mapped, check that the buffer end does not
overflow over the virtual address node space.

Bug 1562361

Change-Id: I3c78ec7380584ae55f1e6bf576f524abee846ddd
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
2015-03-18 12:11:42 -07:00
Konsta Holtta
28476a5b13 gpu: nvgpu: create new nvgpu ioctl header
Move nvgpu ioctls from the many user space interface headers to a new
single nvgpu.h header under include/uapi. No new code or replaced names
are introduced; this change only moves the definitions and changes
include directives accordingly.

Bug 1434573

Change-Id: I4d02415148e437a4e3edad221e08785fac377e91
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/542651
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:11:33 -07:00
Konsta Holtta
719923ad9f gpu: nvgpu: rename gpu ioctls and structs to nvgpu
To help remove the nvhost dependency from nvgpu, rename ioctl defines
and structures used by nvgpu such that nvhost is replaced by nvgpu.
Duplicate some structures as needed.

Update header guards and such accordingly.

Change-Id: Ifc3a867713072bae70256502735583ab38381877
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/542620
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:11:33 -07:00
Konsta Holtta
91ada92f61 gpu: nvgpu: ioctl support flags in gpu characteristics
Expose supported nvgpu ioctls to userspace via bits in the flags field
of nvhost_gpu_characteristics; currently define two bits for special
memory allocation support.

Bug 1539747

Change-Id: I1bc9333b12825d07a00b7a4136ae9d35816a5855
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/495942
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:11:19 -07:00
Konsta Holtta
1d026d1f77 gpu: nvgpu: check dma_buf_get retval with IS_ERR
dma_buf_get returns PTR_ERRs, so fix checking for null to proper IS_ERR
in gk20a_vm_map_buffer. Buffer mapping from user space with ioctls would
also have paniced here if an improper handle would be passed.

Change-Id: I245fe41cd209e49fc9265e56340c1c8215ffb1d2
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/498320
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:11:15 -07:00
Terje Bergstrom
1bc3b3436f gpu: nvgpu: Use pgsz_idx instead of page_size
Alloc space writes the page size to a field that requires pgsz_idx.
That can cause corruption in internal kernel structures.

Clear_sparse treated a parameter as page size instead of index.

Bug 1549451

Change-Id: I73ce17b99aae6865056facce72d2ab9ca8b3f81d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/495692
2015-03-18 12:11:11 -07:00
Terje Bergstrom
8be2f2bf4c gpu: nvgpu: gm20b: Regenerate clock gating lists
Regenerate clock gating lists. Add new blocks, and takes them into
use. Also moves some clock gating settings to be applied at the
earliest possible moment right after reset.

Change-Id: I21888186c200f7a477c63bd3332e8ed578f63741
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/457698
2015-03-18 12:11:09 -07:00
Aingara Paramakuru
1fd722f592 gpu: nvgpu: support gk20a virtualization
The nvgpu driver now supports using the Tegra graphics virtualization
interfaces to support gk20a in a virtualized environment.

Bug 1509608

Change-Id: I6ede15ee7bf0b0ad8a13e8eb5f557c3516ead676
Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-on: http://git-master/r/440122
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:11:01 -07:00
Deepak Nibade
69e0cd3dfd gpu: nvgpu: manage phys pages at runtime
Current implementation is based on config GK20A_PHYS_PAGE_TABLES
to have APIs to create/free/map/unmap phys pages

Remove this config based implementaion and move the APIs so that
they are called at runtime based on tegra_platform_is_linsim()

In generic APIs, we first check if platform is linsim and if it
is then we forward the call to phys page specific APIs

Change-Id: I23eb6fa6a46b804441f18fc37e2390d938d62515
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/488843
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:11:00 -07:00
Kevin Huang
87373abc95 gpu: nvgpu: gm20b: use gpc_mmu to check debug mode
Bug 1534793

Change-Id: I8a4c35914b58dd13a7c10c668de9d4662d947d8c
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/441377
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:10:53 -07:00
Kevin Huang
62e80a189c gpu: nvgpu: clear sparse in space free
Gk20a unmaps the addresses binding to dummy page to clear sparse.
On Gm20b, we need to free the allocated page table entry for sparse
memory.

Bug 1538384

Change-Id: Ie2409ab016c29f42c5f7d97dd7287b093b47f9df
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/448645
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:10:52 -07:00
Lauri Peltonen
c60a300c4a gpu: nvgpu: Attach compression state to dma-buf
Bug 1509620

Change-Id: I694fe43ef5d1f4f329d997a3d60e006785374cc3
Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com>
Reviewed-on: http://git-master/r/439849
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:10:40 -07:00
Arto Merilainen
4cb6f6b357 gpu: nvgpu: Add helpers for backing store access
This patch adds mm helpers to access compression backing store
from in-kernel shader.

Bug 1409151

Change-Id: Icb4f6dc0b5a35fdb97bc4221ab3657866f775fae
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/440263
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Lauri Peltonen <lpeltonen@nvidia.com>
GVS: Gerrit_Virtual_Submit
2015-03-18 12:10:32 -07:00
Terje Bergstrom
2c15c3265b gpu: nvgpu: Bump unmap retries if not silicon
In simulation and emulation 50ms is not enough to ensure a job is
complete. Bump it to 5s when not running on silicon.

Bug 1510751

Change-Id: I90883b70ce2a75a8f07344f713d647b3fa0d0c7d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/432044
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chris Dragan <kdragan@nvidia.com>
Tested-by: Chris Dragan <kdragan@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
2015-03-18 12:10:20 -07:00