Commit Graph

14 Commits

Author SHA1 Message Date
Seshendra Gadagottu
a91535e3a3 gpu: nvgpu: avoid gr_falcon dependency outside gr
Basic units like fifo, rc are having dependency on
gr_falcon. Avoided outside gr units dependency on gr_falcon
by moving following functions to gr:

int nvgpu_gr_falcon_disable_ctxsw(struct gk20a *g,
			struct nvgpu_gr_falcon *falcon); ->
int nvgpu_gr_disable_ctxsw(struct gk20a *g);

int nvgpu_gr_falcon_enable_ctxsw(struct gk20a *g,
			struct nvgpu_gr_falcon *falcon); ->
int nvgpu_gr_enable_ctxsw(struct gk20a *g);
int nvgpu_gr_falcon_halt_pipe(struct gk20a *g); ->
		int nvgpu_gr_halt_pipe(struct gk20a *g);

HALs also moved accordingly and updated code to reflect this.

Also moved following data back to gr from gr_falcon:
struct nvgpu_mutex ctxsw_disable_mutex;
int ctxsw_disable_count;

JIRA NVGPU-3168

Change-Id: I2bdd4a646b6f87df4c835638fc83c061acf4051e
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100009
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2019-04-23 05:04:44 -07:00
Thomas Fleury
e69b5f75ba gpu: nvgpu: move sync cmdbuf to hal/sync
Moved
- common/sync/sema_cmdbuf_gk20a.c -> hal/sync/sema_cmdbuf_gk20a.c
- common/sync/sema_cmdbuf_gk20a.h -> hal/sync/sema_cmdbuf_gk20a.h
- common/sync/sema_cmdbuf_gv11b.c -> hal/sync/sema_cmdbuf_gv11b.c
- common/sync/sema_cmdbuf_gv11b.h -> hal/sync/sema_cmdbuf_gv11b.h
- common/sync/syncpt_cmdbuf_gk20a.c -> hal/sync/syncpt_cmdbuf_gk20a.c
- common/sync/syncpt_cmdbuf_gk20a.h -> hal/sync/syncpt_cmdbuf_gk20a.h
- common/sync/syncpt_cmdbuf_gv11b.c -> hal/sync/syncpt_cmdbuf_gv11b.c
- common/sync/syncpt_cmdbuf_gv11b.h -> hal/sync/syncpt_cmdbuf_gv11b.h

Updated makefiles and #include directives.

Jira NVGPU-1984

Change-Id: I5df008512a9243572081a89310d12a77c2354924
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2101322
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Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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2019-04-22 23:54:35 -07:00
Seema Khowala
509fd2c93a gpu: nvgpu: rename fifo_gv100.[ch]
Rename
fifo_gv100.[ch] -> hal/fifo/fifo_intr_gv100.[ch]

JIRA NVGPU-3144

Change-Id: I0add5ac7889ba98d5cf53f939f704faf92aa20eb
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2101278
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2019-04-22 15:25:52 -07:00
Seema Khowala
bdfc26af8b gpu: nvgpu: move preempt code to common/fifo and hal/fifo
Move chip specific preempt code to hal/fifo
Move non-chip specific preempt code to common/fifo

Remove fifo.get_preempt_timeout

Rename gk20a_fifo_get_preempt_timeout -> nvgpu_preempt_get_timeout
Rename gk20a_fifo_preempt -> nvgpu_preempt_channel

Add fifo.preempt_trigger hal for issuing preempt
Add fifo.preempt_runlists_for_rc hal for preempting runlists during rc
Add fifo.preempt_poll_pbdma hal

Add nvgpu_preempt_poll_tsg_on_pbdma to be called from rc

JIRA NVGPU-3144

Change-Id: Idb089acaa0c6ca08de17487c3496459a61f0bcd4
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100819
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2019-04-22 15:25:29 -07:00
Philip Elcan
edaddb9bb2 gpu: nvgpu: create nvgpu.common.hal.clk
Create unit nvgpu.common.hal.clk in by moving clk_*.[ch] files to
hal/clk path. Also update makefiles and include files to match.

JIRA NVGPU-2020

Change-Id: Ied217cfac2b000a2d22eda582d6030d0479b1310
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2101400
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2019-04-22 14:15:22 -07:00
Vinod G
8880c82111 gpu: nvgpu: move gk20a_gr_isr to hal
Move gk20a_gr_isr function to stall_isr hal in gr.intr unit.
Move all static functions accessed in gk20a_gr_isr function
to gr_intr file from gr_gk20a file.

Update mc hal functions to use g->ops.gr.intr.stall_isr

JIRA NVGPU-1891
JIRA NVGPU-3016

Change-Id: If379348eef863b8d794a726b98e190ebe8585cb2
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100670
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2019-04-20 13:44:02 -07:00
Vinod G
14a71cb25a gpu: nvgpu: add esr_bpt_pending_events hal
Add esr_bpt_pending_events hal to report the type of
esr_bpt_pending_events to isr to process.

Add hal functions in gr instead of moving to gr.intr unit, as it
is part of non safety code.

JIRA NVGPU-1891

Change-Id: I70d75686042f97aa0e820d7982e95354971c9074
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100669
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2019-04-20 13:43:53 -07:00
Seema Khowala
7a440fb721 gpu: nvgpu: move engine functions
Move engine functions from fifo_gv11b.c to common/fifo/engines

Add fifo.mmu_fault_id_to_pbdma_id hal

JIRA NVGPU-1313

Change-Id: I6a6ac385a64c4908098ea9e483544b1e1b2d0c58
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2098950
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2019-04-19 14:45:19 -07:00
Thomas Fleury
5e12623785 gpu: nvgpu: add HALs for num lce and bar2 fault
Added the following HALs:
- top.get_num_lce
- ce.mthd_buffer_fault_in_bar2_fault

Jira NVGPU-1992

Change-Id: Ib0bd8c862d1f847621c1c04ed3459d17f533009d
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2099089
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2019-04-19 13:55:53 -07:00
Thomas Fleury
1160f083d4 gpu: nvgpu: move ce code to common/ce and hal/ce
Merged gk20a_ce_delete_context and gk20a_ce_delete_context_priv.

Renamed
- gk20a_init_ce_support -> nvgpu_ce_init_support
- gk20a_ce_destroy -> nvgpu_ce_destroy
- gk20a_ce_suspend -> nvgpu_ce_suspend
- gk20a_ce_create_context -> nvgpu_ce_create_context
- gk20a_ce_delete_context -> nvgpu_ce_delete_context
- gk20a_ce_execute_ops -> nvgpu_ce_execute_ops
- gk20a_ce_prepare_submit -> nvgpu_ce_prepare_submit
- gk20a_ce_put_fences -> nvgpu_ce_put_fences
- gk20a_ce_delete_gpu_context -> nvgpu_ce_delete_gpu_context
- gk20a_ce_get_method_size -> nvgpu_ce_get_method_size
- gk20a_gpu_ctx -> nvgpu_ce_gpu_ctx
- gk20a_gpu_ctx_from_list -> nvgpu_ce_gpu_ctx_from_list
- gk20a_ce_app -> nvgpu_ce_app
- gk20a_ce_debugfs_init -> nvgpu_ce_debugfs_init
- gk20a_get_valid_launch_flags -> nvgpu_ce_get_valid_launch_flags
- gk20a_ce2_isr -> gk20a_ce2_stall_isr
- gp10b_ce_isr -> gp10b_ce_stall_isr
- gv11b_ce_isr -> gv11b_ce_stall_isr

Inlined
- ce*_nonblockpipe_isr
- ce*_blockpipe_isr
- ce*_launcherr_isr

Added ce_priv.h for ce private definitions.

Moved files to common/ce and hal/fifo/ce
- ce2.c -> common/ce2/ce.c
- ce2_gk20a.c -> hal/ce/ce2_gk20a.c
- ce2_gk20a.h -> hal/ce/ce2_gk20a.h
- ce_gp10b.c -> hal/ce/ce_gp10b.c
- ce_gp10b.h -> hal/ce/ce_gp10b.h
- ce_gv11b.c -> hal/ce/ce_gv11b.c
- ce_gv11b.h -> hal/ce/ce_gv11b.h

Updated makefiles and #include directives

Jira NVGPU-1992

Change-Id: Ia6064bf51b7a254085be43a112d056cb6fb6c3b2
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2093503
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2019-04-19 13:55:11 -07:00
Thomas Fleury
7fb397b0b3 gpu: nvgpu: add format_gpfifo_entry HAL for pbdma
Removed dependency on pbdma hw headers in ce2, cde and submit.

Added the following HAL to format gpfifo entries:
- pbdma.format_gpfifo_entry

Jira NVGPU-1992
Jira NVGPU-1990

Change-Id: I322d6bcd832b0ea5bbe2c2871b8f96b2793d8a65
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2093502
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2019-04-19 13:54:56 -07:00
Deepak Nibade
d0907087c1 gpu: nvgpu: remove gfxp_wfi_timeout_count/unit fields from gr.ctx_vars struct
gfxp_wfi_timeout_count/unit fields were stored in gr_gk20a.ctx_vars
struct so that any user could configure them through sysfs nodes

But the sysfs nodes are legacy and not being actively used by anyone.
Hence delete the sysfs nodes to configure these fields.

Since the gfxp timeout unit/count can now be statically programmed,
make following changes
- remove g->ops.gr.init_gfxp_wfi_timeout_count() hal
- remove g->ops.gr.get_max_gfxp_wfi_timeout_count() hal
- update g->ops.gr.init.preemption_state() hals to configure the values
  using macros instead of caller passing the values
- update g->ops.gr.init.gfxp_wfi_timeout() hals to configure the values
  using macros instead of caller passing the values

Finally, we don't need to store gfxp_wfi_timeout_count/unit fields
anymore, hence delete them from gr_gk20a.ctx_vars

Jira NVGPU-3112

Change-Id: Idbe5ab3053228dd177aca253545aac36d38ca8ad
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100219
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Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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2019-04-19 08:44:44 -07:00
Philip Elcan
37253f8ccb gpu: nvgpu: init: cleanup headers
Remove unnecessary header files from nvgpu.common.hal.init unit.

Change-Id: I60f979cd700c3a8fc5fd78cfcac0298e1766ac25
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2098916
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2019-04-18 15:56:46 -07:00
Philip Elcan
f0640b9d10 gpu: nvgpu: create nvgpu.common.hal.init unit
Move hal init from chip-specific paths to hal/init. Update makefiles and
include paths to match.

JIRA NVGPU-2023

Change-Id: I810c817bb0ba83dcf5ed4d05df502e85c2fd77df
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2098915
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2019-04-18 15:56:31 -07:00