nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-23 18:16:01 +03:00
Code Issues Packages Projects Releases Wiki Activity
2,340 Commits 57 Branches 84 Tags
a94b4bcde9b88e856d4b6f2bcb9e0e23942a69cc
Commit Graph

2340 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Deepak Nibade
095bd5e59d gpu: nvgpu: mask hww_warp_esr for gp10b 
Add API gp10b_mask_hww_warp_esr() to mask
hww_warp_esr appropriately on gp10b

Bug 200156699

Change-Id: I451b5e949bd4e6d286e5d0c7cd7616e6cfaf3ea9
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/927129
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:10 +05:30
Adeel Raza
f17e0d822b gpu: nvgpu: gp10b: add ECC support 
Add ECC exception handling support for SM, TEX, and LTC.

Bug 1635727
Bug 1637486

Change-Id: I8862ead5784f48742355432ec07c71a82b1b6735
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/935362
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2016-12-27 15:22:10 +05:30
Seshendra Gadagottu
4c5bc9c93b gpu: nvgpu: gp10b: clean-up pmu init operations 
Removed unwanted initlization of function pointer.

Bug 200157852

Change-Id: I3b44ccce366f1b72c3ff769a7b9ab350bb2c0066
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/843218
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:10 +05:30
Seshendra Gadagottu
acc62a236f gpu: nvgpu: gp10b: enable power gating 
Enable engine level power gating(elpg)

Bug 200144583

Change-Id: I66f3be841625c2c9e07cafbf19af8f1dbdbfd390
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/818637
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:10 +05:30
Seshendra Gadagottu
d730381f93 gpu: nvgpu: gp10b: add delay cycles before engine gating 
For copy engine, add 16 clock cycle delay
before engine clock gating.

Bug 1717152

Change-Id: Ife92299c052f44000bc0d900f0129a2eab13f3b5
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/998408
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:10 +05:30
Seshendra Gadagottu
b8db86a6b6 gpu: nvgpu: gp10b: enable gradual slowdown 
Enable gradual slowdown for gp10b and also correct
thermal slowdown factors with extended mode.

Bug 1719974

Change-Id: I31a5d7df71c98135273a980c49b70bc76fac0b40
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/933279
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:10 +05:30
Konsta Holtta
1ec6d2b6d6 gpu: nvgpu: bitmap allocator for comptags 
Restore comptags to be bitmap-allocated, like they were before we had
the buddy allocator.

Bug 200145635

Change-Id: I681493871096f437014b7eca1182fefbaf7f6a74
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/839240
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:10 +05:30
Richard Zhao
5dcbe39a71 gpu: nvgpu: enable semaphore acquire timeout for gp10b 
It'll detect dead semaphore acquire. The worst case is when
ACQUIRE_SWITCH is disabled, semaphore acquire will poll and
consume full gpu timeslicees.

The timeout value is set to half of channel WDT.

Bug 1636800

Change-Id: Idbd4bfa52981e8a849b62a168e3a6828330112f5
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/928830
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:10 +05:30
Terje Bergstrom
03afa9b060 gpu: nvgpu: gp10b: Refresh regops whitelist 
Context & global whitelists are same, so delete second copy. Update
the list.

Bug 200164983

Change-Id: I440ce04316120b8128baeabc002c55436cf41d5b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/931178
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sandarbh Jain <sanjain@nvidia.com>
Tested-by: Sandarbh Jain <sanjain@nvidia.com>
 2016-12-27 15:22:10 +05:30
Aingara Paramakuru
36fa64cab4 gpu: nvgpu: vgpu: update interface to free GR ctx 
The server only releases ownership of the ctxsw buffer mappings
after the GR ctx has been released. Update the sequence to
account for this.

JIRA VFND-1117
Bug 1708163

Change-Id: I3aed015805b4ca51433e7d37ad32de2f8353999f
Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-on: http://git-master/r/922817
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
 2016-12-27 15:22:10 +05:30
David Li
97ba307f51 gpu: nvgpu: fix setting gr_pd_ab_dist_cfg1_r() 
gr_*__set_alpha_circular_buffer_size() left max_batches field of
  gr_pd_ab_dist_cfg1_r as 0 which results in too many alpha beta
  transitions and poor performance when tessellation or geometry
  shaders are used

Change-Id: Ic3673f45b60674b3527641a6fdda0cedc6861db5
Signed-off-by: David Li <davli@nvidia.com>
Reviewed-on: http://git-master/r/840079
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:10 +05:30
David Li
6430abceef gpu: nvgpu: gp10b: fix set_circular_buffer_size 
It didn't set gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r
  causing a GPU MMU fault when used.

Bug 200141640
Bug 200141981
Bug 200141640

Change-Id: I8b9f71e480553ead2827ff1f1dde2ba2e6efe697
Signed-off-by: David Li <davli@nvidia.com>
Reviewed-on: http://git-master/r/807694
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:09 +05:30
Terje Bergstrom
d44b5ecc30 gpu: nvgpu: Recreate HW headers 
Add gradual slowdown registers, and fix names for L2 flush registers.

Change-Id: If085c4febef494ae299d2147ca5201cd373bee0b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/839369
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
 2016-12-27 15:22:09 +05:30
Terje Bergstrom
108c0ac8bd gpu: nvgpu: gp10b: Add tile caching registers 
Add tile caching registers to access map.

Bug 1692373

Change-Id: Ic95fce02c564fa8d5556543a744c9828b542fb1f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/812352
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
 2016-12-27 15:22:09 +05:30
Terje Bergstrom
fd624a1f4e gpu: nvgpu: gp10b: Install gp10b access map 
Bug 1692373

Change-Id: I63bb1f8a40fe5d2c7b61440c989b78e4cb3ece98
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/812351
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
 2016-12-27 15:22:09 +05:30
Seshendra Gadagottu
1cde817120 gpu: nvgpu: t18x: make gp10b_freq_table static 
Make gp10b_freq_table static to fix sparse warning

Bug 200088648

Change-Id: Ibaaabd145e37685e049ac3a49e2b276fb6545d0e
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/837421
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:09 +05:30
Mahantesh Kumbar
b76acb0ef6 gpu: nvgpu: ELPG prod values update 
Bug 200151348

Change-Id: I44851b69adfe9c6bf5d4c897730d6da7df9bedd8
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/836877
(cherry picked from commit 69de3f3c439f544fd5f9223f5663010f5ec80193)
Reviewed-on: http://git-master/r/837228
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:09 +05:30
Seshendra Gadagottu
1146dbae18 gpu: nvgpu: gp10b: add support for freq scaling 
Add support for gp10b freq scaling.

Bug 200147662

Reviewed-on: http://git-master/r/816962
(cherry picked from commit 62de7dba758e46ee80c896dcfcbccb0f8b979438)

Change-Id: I71ddfa394d490c002761d2a8bbb95090a4c0e799
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/834758
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:09 +05:30
Sami Kiminki
4181fa7185 gpu: nvgpu: User-space managed address space support (gp10b) 
Tell gk20a_init_vm() that bar2 VM is kernel-managed.

Bug 200077571

Change-Id: I151c540a6dec76238e7959f745cfca280927f2d4
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: http://git-master/r/746803
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:09 +05:30
Seshendra Gadagottu
ac335e6fb5 gpu: nvgpu: gp10b: correct initial gpcclk rate 
Set initial gpcclk rate to 1GHz.

Bug 200151332

Reviewed-on: http://git-master/r/834113
(cherry picked from commit 9ed69164da7afeec20c3a557885f74db4cbea9cb)

Change-Id: I85107eb5852b25977b30663f6ae173b271ecafeb
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/834322
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:09 +05:30
Terje Bergstrom
e390f6e95a gpu: nvgpu: ZBC update without idle 
Do ZBC updates without forcing engine idle first.

Bug 1698013

Change-Id: I188563dd60ba511b087e9b9bdacd7f9445efd7a4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/829146
 2016-12-27 15:22:09 +05:30
Terje Bergstrom
1dde902b50 Revert "gpu: nvgpu: gp10b: Force always SMMU bypass" 
This reverts commit cc9bd2dc24f562e97a87641e7436594fd3b469f2.

Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Change-Id: Ic4493bc7b71a2ebfb49644c91b34222dd15a9be1
Reviewed-on: http://git-master/r/830854
GVS: Gerrit_Virtual_Submit
 2016-12-27 15:22:09 +05:30
Alex Waterman
528c08b501 arm64: tegra: dts: Use new SID dt-bindings 
Use bindings more specific to the ARM SMMU.

Change-Id: I0e2df8e8e7bfa51036a84e923fa06e42bbed3cd7
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/812438
(cherry picked from commit 98cb259c87e9531b0a21dfd3132a3f3db07ff6f0)
Reviewed-on: http://git-master/r/831515
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>
 2016-12-27 15:22:09 +05:30
Aingara Paramakuru
9ab9436268 gpu: nvgpu: gp10b: map GfxP buffers as GPU cacheable 
Some of the allocated buffers are used during normal graphics
processing. Mark them as GPU cacheable to improve performance.

Bug 1695718

Change-Id: I71d5d1538516e966526abe5e38a557776321597f
Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-on: http://git-master/r/827087
(cherry picked from commit 60b40ac144c94e24a2c449c8be937edf8865e1ed)
Reviewed-on: http://git-master/r/828493
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:09 +05:30
Terje Bergstrom
f4b2a02b68 gpu: nvgpu: gp10b: Add L2 clean comptags regs 
Bug 1698618

Change-Id: I5bad939d94171d2296897260043f0e67e43802e7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/829097
(cherry picked from commit a067cfeb8dda03641ba981d86bef93fa9041e18e)
Reviewed-on: http://git-master/r/829414
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2016-12-27 15:22:09 +05:30
Richard Zhao
b7de6b004b gpu: nvgpu: vgpu: set correct page size index for gp10b 
VM server only know big page and small page, so convert
gmmu_page_size_kernel to according page size index.

JIRA VFND-890

Change-Id: Id1f932752b8ca33d14635ac9d71019364aa89dc4
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/816359
(cherry picked from commit 5bfc4a2a55889f5457bd34aa06861c042ee67421)
Reviewed-on: http://git-master/r/827131
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
 2016-12-27 15:22:09 +05:30
Terje Bergstrom
de2656300a Revert "gpu: nvgpu: gp10b: Implement sparse PDEs" 
This reverts commit c2707054192b058eec24a52c7f586b030f9ff007. It
introduces regression in T124.

Bug 1702063

Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Change-Id: I8516c0bfe129bb1ac3d7a1983846061df8ae967b
Reviewed-on: http://git-master/r/830787
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
 2016-12-27 15:22:09 +05:30
Seshendra Gadagottu
4ff59992af gpu: nvgpu: gp10b: set ptimer source frequency 
Set platform data with ptimer source frequency.
Removed ptimerscaling10x platform data, and use
ptimer source frequency to calculate ptimerscaling
factor.

Reviewed-on: http://git-master/r/819031
(cherry picked from commit 6849603024943184b0463233bedd95934c353663)

Change-Id: I14b0735fcb602cda2e692f6b842a5ecf469ab724
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/827301
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:09 +05:30
Terje Bergstrom
fb7065a2e4 gpu: nvgpu: gp10b: Implement sparse PDEs 
Change-Id: I260958d8dea1b445f91b8d15bf76d5321bdc76d1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/758653
 2016-12-27 15:22:09 +05:30
Seshendra Gadagottu
313fcdb1d3 gpu: nvgpu: gp10b: update thermal programming 
Add required fileds and values for thermal slow-down
settings in thermal header file and corrected
thermal register programming with correct values.

Bug 1695567

Reviewed-on: http://git-master/r/822200
(cherry picked from commit 859d1bda6a059b321d859c887fab8d51d2caa981)

Change-Id: Id90ebd46bc3d6e4284a91e7f2b775d78502a3eca
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/823013
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:09 +05:30
Seshendra Gadagottu
35e3018be1 gpu: nvgpu: gp10b: support to remove bar2 vm 
Implement function to support bar2 vm clean-up.

Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/814573

Change-Id: If5d884e4e1ed87bec6284719d90e9e1963c69bed
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/815428
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:09 +05:30
Seshendra Gadagottu
242623a0a8 gpu: nvgpu: gp10b: enable clock gating features 
Enable clock gating power features: slcg, blcg and elcg

Bug 200144583

Reviewed-on: http://git-master/r/821149
(cherry picked from commit 1980d443c64e6660e3cd41b8908964c07459dcce)

Change-Id: I6ce813552fa57d0fd14dd7ed6a3d9864c88dc58b
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/818636
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:09 +05:30
Aingara Paramakuru
9320d4711f gpu: nvgpu: vgpu: add interface to alloc ctxsw buffers 
gp10b introduces support for preemption (GfxP and CILP).
Add a new interface to allow allocating buffers needed
to support this functionality.

Bug 1677153

Change-Id: I8578a7b0a4327f3496d852eeb8be5fc778e2c225
Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-on: http://git-master/r/806963
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/817039
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:09 +05:30
Sami Kiminki
428b9eb552 gpu: nvgpu: gp10b: Fix support for new color compression kinds 
Fix support for kinds C32_MS4_4CBRA and C64_MS4_4CBRA. They're both
compressible and ZBC kinds, so mark them as such, too.

Change-Id: Ide09ea79a885361ecfc3c188606799c6b2fbdd2e
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: http://git-master/r/816015
(cherry picked from commit 302b06b76aed5278286487225d6e7280b747d4b3)
Reviewed-on: http://git-master/r/816014
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:09 +05:30
Terje Bergstrom
2643f200cf gpu: nvgpu: gp10b: Use PROD value for FE_GO_IDLE_TIMEOUT 
Add gp10b PROD value for FE_GO_IDLE_TIMEOUT. Use the PROD value
written in gk20a_init_gr_setup_hw() instead of hard coding here.

Change-Id: If3bd981c1c0d9cc8ad19c21c220b7de81fdb529e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/813959
 2016-12-27 15:22:08 +05:30
Deepak Nibade
35b5e65166 gpu: nvgpu: add h/w headers for pbdma_methods 
Bug 200134238

Change-Id: I263a12b7a3a74d1ab07bca03d5dda685b1e4f22f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/815128
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:08 +05:30
Seshendra Gadagottu
9f2d5c97f9 gpu: nvgpu: gp10b: create fault buffer only once 
Create only one instance of replayable fault buffer
mapping.

Change-Id: Id766298f338ce54cfca7510cbb9e4528ef1945a3
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/814615
(cherry picked from commit 422d2ced384220668347dc8422876d75f6e8807d)
Reviewed-on: http://git-master/r/817696
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:08 +05:30
Mahantesh Kumbar
50f5c87f1c gpu: nvgpu: gp10b non-secure gpmu hw init 
call gp10b_init_pmu_setup_hw1 during non-secure boot only.

Change-Id: Ia90474c7c04edd9be029d013f1da5f73de1b5326
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/815843
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:08 +05:30
Terje Bergstrom
fa467827b7 gpu: nvgpu: gp10b: Make CB size and default size same 
We used to allocate 1.5x buffer size. This leads to memory waste, as
we do not set the CB size via SW methods anymore.

Bug 1686189

Change-Id: I45cbdeadc154f59b65138f99f50a72d97511cb78
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/801865
(cherry picked from commit 791f2fe03d16521206649ab90498443e91e284e2)
Reviewed-on: http://git-master/r/815683
 2016-12-27 15:22:08 +05:30
Terje Bergstrom
f1fe07c123 gpu: nvgpu: gp10b: Fix beta CB sizing 
Handle beta CB sizing differences for GfxP versus WFI channels.

Bug 1686189

Change-Id: Icc421eeb8305f7e4156a74c957662f19504ddad7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/801533
(cherry picked from commit 95b9ae4e5f3c29fdb97567d846b9d2139f1a8ec4)
Reviewed-on: http://git-master/r/815682
 2016-12-27 15:22:08 +05:30
Terje Bergstrom
4d3f44849b gpu: nvgpu: gp10b: Report Pascal DMA copy class 
Announce supporting Pascal DMA copy class instead of Maxwell.

Change-Id: Ic0b9d50e7423648c5573857142c86b8a8bc87e35
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/808140
(cherry picked from commit c779975d6b40ecb0780ae4167ab26aed4886c7a7)
Reviewed-on: http://git-master/r/815679
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
 2016-12-27 15:22:08 +05:30
Terje Bergstrom
959756873a gpu: nvgpu: gp10b: Fix spill buffer size 
Spill buffer size is in chunks of 256B. Multiply the size by
granularity to get the size in bytes.

Bug 1686189

Change-Id: I0462293668322645bd1eab190c12faaeb6c316c1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/801344
(cherry picked from commit 4bf6de7d9c9014a9eaeff56b19437d1841d7cfb0)
Reviewed-on: http://git-master/r/815680
 2016-12-27 15:22:08 +05:30
Terje Bergstrom
a982fab351 gpu: nvgpu: gp10b: Fix pagepool max size 
If pagepool size equals max we should use zero. Add the comparison
to do that.

Bug 1686189

Change-Id: I15bd43663550b1089a726c0256b89f849c193e21
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/801526
(cherry picked from commit 9d89ea5ba345b19d2cff86130ba9d3c4c5f07e6e)
Reviewed-on: http://git-master/r/815681
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
 2016-12-27 15:22:08 +05:30
Seshendra Gadagottu
520b461aa7 gpu: nvgpu: gp10b: enable dma for firmware loading 
Bug 1692799

Change-Id: Idf825c954c646f649d85b8fa7f76b5b45150bfe5
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/812442
(cherry picked from commit f72c0738238c3f9a034c6a8b064226f0d7d5dd63)
Reviewed-on: http://git-master/r/813978
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:08 +05:30
Seshendra Gadagottu
8066fc9b7b gpu:nvgpu: gp10b: modify gpmu hw init 
Modify gpmu hwinit to take gp10b specific register offsets in
non-secure GPMU boot path.

Bug 1685722

Change-Id: Id6696fb20c4fd40ee1b168c952a438771721c792
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/812271
(cherry picked from commit b9408892dd08beca5f4b2e056287a2bc28ccff0e)
Reviewed-on: http://git-master/r/813979
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:08 +05:30
Deepak Nibade
8d864432f5 gpu: nvgpu: set wdt timeout for gp10b 
set platform specific channel watchdog timeout to 5s
for gp10b

Bug 200133289

Change-Id: I4478463e22a8167c2fc1235dd9a80e069a27b47c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/811509
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:08 +05:30
Matt Craighead
6f4d1bb2e7 gpu: nvgpu: gp10b: skip powergate if no BPMP 
The powergating APIs only work if the BPMP is running.  Skip
these calls if it's not available, instead of relying on
is_linsim, which doesn't work under all environments.

Change-Id: I34325847b2ebf33c5db2f31111c57d22ed28ef53
Signed-off-by: Matt Craighead <mcraighead@nvidia.com>
Reviewed-on: http://git-master/r/812415
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:08 +05:30
Terje Bergstrom
1ba28cf44d gpu: nvgpu: gp10b: Force always SMMU bypass 
Bug 1688709

Change-Id: If778034225dabbd0f9e6ff843ea6f06011c432bd
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/807030
(cherry picked from commit 32f03899ca689f6af12760afe04cf4c8e60ebba1)
Reviewed-on: http://git-master/r/808243
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
 2016-12-27 15:22:08 +05:30
Seshendra Gadagottu
9fb5c25782 gpu: nvgpu: gp10b: update slcg xbar prod settings 
Bug 1689806

Change-Id: I98ca5fe006ecdf056ac45b15b2dc128929ea4fd5
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/806115
(cherry picked from commit fc15b029187db4f2aba213e89672bd84b5d020cd)
Reviewed-on: http://git-master/r/805482
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:08 +05:30
Vijayakumar
c6766cc798 gpu :nvgpu: gp10b: add ptimer scaling factor as 1x 
bug 1603226

t18x fixes ptimer bug and ticks at 1ns.

Change-Id: I590c94957c93adf70263f81a0cdfcb8dc913639e
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/799989
(cherry picked from commit 44866e195113b0a44ed2513a81dcaaf079c2a5f1)
Reviewed-on: http://git-master/r/707810
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:08 +05:30