Deepak Nibade
a94e6e72e6
gpu: nvgpu: add T18x specific event ids
...
Add CILP preemption started/completed event ids
Bug 200089620
Change-Id: Ie78c9fbe517fd18c4438b6fc06d4c1cf046ba586
Signed-off-by: Deepak Nibade <dnibade@nvidia.com >
Reviewed-on: http://git-master/r/1030777
(cherry picked from commit 065f672020942d377fe3f2388f9daa058406110a)
Reviewed-on: http://git-master/r/1120288
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com >
2016-12-27 15:22:11 +05:30
Sami Kiminki
58adb7385d
gpu: nvgpu: Determine ECC-enabled units for GP10B
...
Determine ECC-enabled units for GP10B by reading fuses/registers.
Bug 1637486
Change-Id: I6431709e3c405d6156dd96438df14d4054b48644
Signed-off-by: Sami Kiminki <skiminki@nvidia.com >
Signed-off-by: Adeel Raza <araza@nvidia.com >
Reviewed-on: http://git-master/r/780992
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com >
Reviewed-on: http://git-master/r/1120463
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com >
2016-12-27 15:22:11 +05:30
Terje Bergstrom
634acd7422
gpu: nvgpu: Expose preemption flags to user space
...
Expose CILP and GFXP flags to user space ioctl
NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX.
Bug 200111328
Change-Id: I10931db2babd3222e308fd491824d95204355ff3
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com >
Reviewed-on: http://git-master/r/748932
GVS: Gerrit_Virtual_Submit
2016-12-27 15:22:06 +05:30
Seshendra Gadagottu
65ef5bc238
gpu:nvgpu: gp10b: update channel_setup_ramfc
...
Enable re-playable faults based on characteristics
flags passed in channel_setup_ramfc.
Bug 1645628
Change-Id: I7176efb3e5af9fefe5fb92cd5b49eb295e8e2c4a
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com >
Reviewed-on: http://git-master/r/743382
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com >
2016-12-27 15:22:06 +05:30
Deepak Nibade
022d8a602c
include: uapi: nvgpu: add flag for IO coherence
...
Add below flag for struct nvgpu_as_map_buffer_ex_args
to specify IO coherence
NVGPU_AS_MAP_BUFFER_FLAGS_IO_COHERENT
Bug 1605653
Change-Id: Id5c8195c37c48cff7ec013c6b4b4d9168d972b8e
Signed-off-by: Deepak Nibade <dnibade@nvidia.com >
Reviewed-on: http://git-master/r/713104
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com >
2016-12-27 15:22:04 +05:30
Kenneth Adams
16c511220e
gpu: nvgpu: t18x, gp10b framework
...
This change adds gp10b to the nvgpu build as
well as enabling CMA for buffer allocation.
Change-Id: Id3d45ad6ffdab14120395952e68b285dd7364c76
Signed-off-by: Ken Adams <kadams@nvidia.com >
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com >
Reviewed-on: http://git-master/r/553324
GVS: Gerrit_Virtual_Submit
2016-12-27 15:22:02 +05:30
