Currently ACR chip specific properties set using HAL ops but
need to move out from HAL ops as ACR unit doesn't access
H/W directly & uses other engines to execute ACR on chip.
To fix used GPUID to init ACR chip specific properties
JIRA NVGPU-2909
Change-Id: I8fa1abcace6f7870bd116d39f94430497d80840b
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2032666
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Currently PMU support enable check is done with multiple
methods which added complexity to know status of PMU
support.
Changed to replace multiple methods with support_pmu
flag to know the PMU support, support_pmu will be updated
at init stage based on platform/chip specific settings
to know the PMU support status.
Cleaned up support_pmu flag check with platform specific
PMU members in multiple places & moved check to
public functions
JIRA NVGPU-173
Change-Id: Ief2c64250d1f78e3b054203be56499e4d1d9b046
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2024024
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Currently clk_arb needs PSTATE to be true for dGPU.
Setting PSTATE only FALSE, causes issue as clk_arb fails.
There is no such dependency of PSTATE on iGPU.
Making it unified with a call to check_clk_arb_support().
This call is implemented based on its dependency in iGPU, dGPU.
check_clk_arb_support returns true if supported, else false.
Jira NVGPU-1948
Change-Id: I108dc12bd6ad8d0e074352080c978b7dda9bee05
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2014775
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
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Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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The support sparse HAL severs only one purpose: return true or false
depending on whether the given chip supports sparse mappings. This
HAL is used to, in turn, program (or not) the
NVGPU_SUPPORT_SPARSE_ALLOCS enabled flag. So instead of having all
this rigmarole to program this flag just program it for all native
GPUs. Then, in the vGPU specific characteristics function disable it
explicitly. This seems to have precedent already.
JIRA NVGPU-1737
JIRA NVGPU-1934
Change-Id: I630928ad656aaffc09fdc6b7fec9fc423aa94c38
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2006796
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pstate s/w setup needs to know offsets of boardobjs present
in PMU super surface to construct boardobj set/get_status
construct.
With SSMD support, boardobj offset will be part of SSMD
lookup table which is part of PMU super surface buffer &
updated by PMU RTOS during init stage.
As SSMD is updated at init stage & SSMD will be ready for nvgpu
to read offsets only when PMU init message is received,
so pstate s/w must wait till PMU is ready to construct
boardobj set/get_status
JIRA NVGPU-1874
Change-Id: I87d840965b92c538f26dbedf458f0c18d1808abc
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2000863
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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Make a physical nvgpu_mem implementation in the common code. This
implementation assumes a single, contiguous, physical range. GMMU
mappability is provided by building a one entry SGT.
Since this is now "common" code the original Linux code has been
moved to commom/mm/nvgpu_mem.c.
Also fix the '__' prefix in the nvgpu_mem function. This is not
necessary as this function, although somewhat tricky, is expected
to be used by arbitrary users within the nvgpu driver.
JIRA NVGPU-1029
Bug 2441531
Change-Id: I42313e5c664df3cd94933cc63ff0528326628683
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1995866
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All slave clock should be quantized as per step size.
TU104 has 15Mhz as step size.
Enable clk_arb without enabling clk_freq_controller.
clk_freq_controller is not needed for Auto use case.
Increase the maxclk only when master is less that slave clock.
This is needed when gpcclk is less than slave P0 min.
Use get_status to get Vim and use it for change sequencer.
Add support for Device Events
Bug 200454682
Bug 2481917
Change-Id: Ie0c404f4b77e41f6a1719b52d6e29a5ac757b41b
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1994831
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaikundanathan S <vaikuns@nvidia.com>
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The container_of() macro used in nvgpu produces the following
set of MISRA required rule violations:
* Rule 11.3 : A cast shall not be performed between a pointer to
object type and a pointer to a different object type.
* Rule 11.8 : A cast shall not remove any const or volatile
qualification from the type pointed to be a pointer.
* Rule 20.7 : Expressions resulting from the expansion of macro
parameters shall be enclosed in parentheses.
Using the same modified implementation of container_of() as that
used in the nvgpu_list_node/nvgpu_rbtree_node routines eliminates
the Rule 11.8 and Rule 20.7 violations and exchanges the Rule 11.3
violation with an advisory Rule 11.4 violation.
This patch uses that same equivalent implementation in two new
(static) functions that are used to replace the reference to
container_of() in nvgpu init code:
* gk20a_from_refcount
It should be noted that replacement functions still contain
potentially dangerous (and non-MISRA compliant code) and that it is
expected that deviation requests will be filed for the new advisory
rule violations accordingly.
JIRA NVGPU-782
Change-Id: I70698c01906872e6bba368b00f5926c4419671d0
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1995743
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Rename __nvgpu_set_enabled() to nvgpu_set_enabled(). The original
double underscore was present to indicate that this function is a
function with potentially unintended side effects (enabling a feature
has wide ranging impact).
To not lose this documentation a comment was added to convey that this
function must be used with care.
JIRA NVGPU-1029
Change-Id: I8bfc6fa4c17743f9f8056cb6a7a0f66229ca2583
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1989434
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With intention to make falcon header free of private data we are making
all falcon struct members (pmu.flcn, sec2.flcn, fecs_flcn, gpccs_flcn,
nvdec_flcn, minion_flcn, gsp_flcn) in the gk20a, pointers to struct
nvgpu_falcon. Falcon structures are allocated/deallocated by
falcon_sw_init & _free respectively.
While at it, remove duplicate gk20a.pmu_flcn and gk20a.sec2_flcn,
refactor flcn_id assignment and introduce falcon_hal_sw_free.
JIRA NVGPU-1594
Change-Id: I222086cf28215ea8ecf9a6166284d5cc506bb0c5
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1968242
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pmu.g & sec2.g were set in nvgpu_falcon_sw_init. They are now set
in nvgpu_early_init_pmu_sw & nvgpu_init_sec2_setup_sw. Pass gk20a
& pmu struct to nvgpu_init_pmu_fw_support like sec2.
pmu_fw_support & sec2_setup_sw are separated from respective init
sequence and now are called earlier since we need ->g member earlier
and most of the setup is sw only.
nvgpu_init_pmu_fw_ver_ops is now being exported.
JIRA NVGPU-1594
Change-Id: I6c71c6730ce06dad190159269e2cc60301f0237b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1968241
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The PMU pstate deinit was invoked part of gpu power off. This frees and clears
the pmgr_pmu struct which causes the pmu remove support to crash when it
tries to access the pmgr_pmu object for freeing up the pmu board objects.
Deferred pstate deinit to nvgpu driver removal as there is no reason for it be
invoked part of prepare poweroff sequence.
JIRA NVGPU-1618
Change-Id: I2eb52000f0732d0abed54946e0843367b119d443
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1971225
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MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.
Adding "U" at the end of the integer literals or casting operands
to have same type of operands when an arithmetic operation is
performed.
This fixes violations where an arithmetic operation is performed on
signed and unsigned int types.
JIRA NVGPU-992
Change-Id: I27e3e59c3559c377b4bd3cbcfced90fdf90350f2
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1921459
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
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