5 Commits

Author	SHA1	Message	Date
rmylavarapu	8daafcbae8	gpu: nvgpu: Restructuring clk.h into different units ... Changes: 1) Separated clk.h which is in /nvgpu/include/pmu into different units 2) Renamed global functions Intention: At present /nvgpu/include/pmu/clk.h consists of structures and functions of different clock units. It is difficult to work on individual clk units if this file is not separated into individual units. All stucts and functions in clk.h are seperated into different clk units. Individual private clk units were not touched. Post this patch, the sebsequent patches would make changes in the individual clk units. NVGPU-2707 Change-Id: I7bf9fab38a73bceb451291530a67c70ed343b0cb Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2021704 Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-02-19 01:55:54 -08:00
Philip Elcan	99ed40b7fb	gpu: nvgpu: clk: fix MISRA 10.3 issues for size_t ... MISRA Rule 10.3 prohibits implicit casting of objects to a different type. This change addresses a number of MISRA 10.3 violations in clk_domain.c where size_t values were being implicitly cast to u16. JIRA NVGPU-1008 Change-Id: If2dc6c6a288fe4b16425a210bc6d76bbef2ce019 Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2001224 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-01-23 13:55:12 -08:00
Philip Elcan	2cff6844fb	gpu: nvgpu: clk: use explicit BIT32 macro ... Use the BIT32() macro to create 32 bit values when assigning to a u32. This avoids MISRA 10.3 violations for assigning different types to a u32. JIRA NVGPU-1008 Change-Id: I0b50c3cf476737d38c943ecc12c4f17f9ba9ddb8 Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2001223 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-01-23 13:55:08 -08:00
Philip Elcan	968db82a65	gpu: nvgpu: clk: fix incorrect casts in returns ... Remove the u32 casting for return values in functions whose return type is int. JIRA NVGPU-1008 Change-Id: I87d4e3a4f8530f45b59a1f612180b295c5238b28 Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2001222 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-01-23 13:55:04 -08:00
Terje Bergstrom	dce78f7332	gpu: nvgpu: Move PMU code to common/pmu ... Move code interfacing with PMU tasks to common/pmu. JIRA NVGPU-961 Change-Id: Ie62611b0ffe1196d4bfdc740e03017e1894a834f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1950991 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-01-10 20:09:55 -08:00