Commit Graph

26 Commits

Author SHA1 Message Date
Konsta Hölttä
b3d16b23d5 gpu: nvgpu: extract priv cmdbuf from channel.c
Move private command buffer related functionality to priv_cmdbuf.c. This
is used only for kernel mode submits, so it makes sense to group it out,
and the priv cmdbuf stuff is used also by things that don't care about
channels.

Jira NVGPU-4548

Change-Id: Idbb42e3ed3984e16c654bb9aa2b7564b780048a4
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2323146
(cherry picked from commit bb67bfc7ab8e87236f31bc4f6c80dab042609f21)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2328406
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
52835c39ae gpu: nvgpu: do not skip completed syncpt prefences
A corner case has existed since ancient times for syncpoint-backed
prefences to not cause a gpu wait if the fence is found to be completed
in the submit path. This adds some unnecessary complexity, so don't
check for completion in software. Let the gpu "wait" for these
known-to-be-trivial waits too. Necessary priv cmdbuf space has been
allocated anyway.

Originally nvhost had 16-bit fences which would wrap around relatively
quickly, so waiting for an old fence could have looked like waiting for
a fence that will expire long in the future. With 32-bit thresholds,
this hasn't been the case for several Tegra generations anymore, and
nvhost doesn't ignore waits like this either.

The wait priv cmdbuf in submit path can still be missing even with a
prefence supplied because the Android sync framework supports sync fds
that contain zero fences inside; this can happen at least when merging
fences that have all been expired. In such conditions the wait cmdbuf
wouldn't even get allocated.

[this is squashed with commit 8b3b0cb12d118 (gpu: nvgpu: allow no wait
cmd with valid input fence) from
https://git-master.nvidia.com/r/c/linux-nvgpu/+/2325677]

Jira NVGPU-4548

Change-Id: Ie81fd8735c2614d0fedb7242dc9869d0961610eb
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2321762
(cherry picked from commit 8f3dac44934eb727b1bf4fb853f019cf4c15a5cd)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2324254
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
2d9b839f21 gpu: nvgpu: remove user sync related apis
Set safe state and get syncpt address in the kernel submission tracking
syncs was implemented for userspace syncs. Now that it's clear that the
user sync object provides them, there are no users left for these APIs.
Remove them.

Jira NVGPU-4548

Change-Id: I58e04162dee55bb8d8547c9252033f40ed908144
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2321950
(cherry picked from commit a95c8f7ace562a11ca235d71496d3a7ce150bc7d)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2324251
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
4f80c6b8a9 gpu: nvgpu: add channel_user_syncpt
Refactor user managed syncpoints out of the channel sync infrastructure
that deals with jobs submitted via the kernel api. The user syncpt only
needs to expose the id and gpu address of the reserved syncpoint. None
of the rest (fences, priv cmdbufs) is needed for that, so it hasn't been
ideal to couple with the user-allocated syncpts.

With user syncpts now provided by channel_user_syncpt, remove the
user_managed flag from the kernel sync api.

This allows moving all the kernel submit sync code to be conditionally
compiled in only when needed, and separates the user sync functionality
in a more clear way from the rest with a minimal API.

[this is squashed with commit 5111caea601a (gpu: nvgpu: guard user
syncpt with nvhost config) from
https://git-master.nvidia.com/r/c/linux-nvgpu/+/2325009]

Jira NVGPU-4548

Change-Id: I99259fc9cbd30bbd478ed86acffcce12768502d3
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2321768
(cherry picked from commit 1095ad353f5f1cf7ca180d0701bc02a607404f5e)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2319629
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
46761356e5 gpu: nvgpu: make channel sync ops const
The function pointers for the syncpoint and semaphore implementations of
struct nvgpu_channel_sync do not change in runtime. Make this more
explicit by having the pointers in predefined private structures. Each
instance of a sync (which there are one per open channel) gets a pointer
to an ops structure instead of a list of all the individual ops.

Jira NVGPU-4548

Change-Id: I361b74bdfe32470203760d11c30e048cb4d20b77
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2318242
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
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2020-12-15 14:13:28 -06:00
Vedashree Vidwans
f2446737fd gpu: nvgpu: fifo: add coverage & traceability
This patch adds new channel and sync test to improve coverage. This
patch also updates SWUTs target tag to increase function traceability
and updates test type.

Jira NVGPU-4817

Change-Id: I52a7fa27f61e7e465d2ede25b92745413f17e50b
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2280963
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Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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2020-12-15 14:13:28 -06:00
Adeel Raza
fd870b300e gpu: nvgpu: rename nvhost_dev to nvhost
A couple of structure member variables were named "nvhost_dev". This
causes a name conflict with a structure name. MISRA frowns upon name
conflicts. Therefore, rename the member variables to "nvhost".

JIRA NVGPU-3873

Change-Id: I4d35eb2d121b3c17499055d8781a61641594811e
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2262190
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2020-12-15 14:10:29 -06:00
Adeel Raza
26af1c2270 gpu: nvgpu: MISRA integer fixes
Apply various MISRA integer related fixes. Some fixes simply required
adding a "U" suffix to integer constants. Other fixes were more
complicated and required breaking up complex composite expressions into
multiple smaller expressions.

JIRA NVGPU-3873

Change-Id: Id8a08a17d1cf9e20193bd3e4f2d4104774d81767
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2262189
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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2020-12-15 14:10:29 -06:00
Adeel Raza
eb0b0c78d4 gpu: nvgpu: sync: remove snprintf usage
snprintf() usage is banned by MISRA because it uses variable arguments.
Replace snprintf() with other string operations.

JIRA NVGPU-3873

Change-Id: I22205f91500c997c155fe1759ccea90b3f481d59
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2262188
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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2020-12-15 14:10:29 -06:00
ddutta
83103cdcca gpu: nvgpu: move set_min_max out of safety build
nvgpu_channel_sync_set_min_eq_max is not used as part of the safety
build and hence is moved out. channel_sync_syncpt_set_min_eq_max is
also moved out as a part of the above function.

Also add a branch coverage for the case when g->disable_syncpoints is
set to true.

Jira NVGPU-913

Change-Id: I2512d01e105551732aad63b2800bb4cb6d913cb2
Signed-off-by: ddutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2263003
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
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2020-12-15 14:10:29 -06:00
Debarshi Dutta
037c5761e7 gpu: nvgpu: handle syncpoint buffer alloc failure
Add check for syncpoint buffer allocation failure in the function
nvgpu_channel_sync_syncpt_create. Return NULL if the allocation fails.

Also, put a reference to the syncpoint allocated if the above
buffer allocation fails.

Change-Id: I56ab03df3b37a3c8148ee17ec6a7829686e44de6
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2247637
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2020-12-15 14:10:29 -06:00
dinesh
25abe6a352 gpu: nvgpu: Compile out linux nvhost
This is added to compile out some non safety code from safety build.

JIRA NVGPU-4146

Change-Id: Ie2b05f7c1bf1d0400184ae95d39103828c28de1e
Signed-off-by: dinesh <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2217415
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
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2020-12-15 14:10:29 -06:00
Debarshi Dutta
f6c96f620f gpu: nvgpu: add CONFIG_NVGPU_KERNEL_MODE_SUBMIT flag
The following functions belong to the path of kernel_mode submit and
the flag CONFIG_NVGPU_KERNEL_MODE_SUBMIT is used to compile these out
of safety builds.

channel_gk20a_alloc_priv_cmdbuf
channel_gk20a_free_prealloc_resources
channel_gk20a_joblist_add
channel_gk20a_joblist_delete
channel_gk20a_joblist_peek
channel_gk20a_prealloc_resources
nvgpu_channel
nvgpu_channel_add_job
nvgpu_channel_alloc_job
nvgpu_channel_alloc_priv_cmdbuf
nvgpu_channel_clean_up_jobs
nvgpu_channel_free_job
nvgpu_channel_free_priv_cmd_entry
nvgpu_channel_free_priv_cmd_q
nvgpu_channel_from_worker_item
nvgpu_channel_get_gpfifo_free_count
nvgpu_channel_is_prealloc_enabled
nvgpu_channel_joblist_is_empty
nvgpu_channel_joblist_lock
nvgpu_channel_joblist_unlock
nvgpu_channel_kernelmode_deinit
nvgpu_channel_poll_wdt
nvgpu_channel_set_syncpt
nvgpu_channel_setup_kernelmode
nvgpu_channel_sync_get_ref
nvgpu_channel_sync_incr
nvgpu_channel_sync_incr_user
nvgpu_channel_sync_put_ref_and_check
nvgpu_channel_sync_wait_fence_fd
nvgpu_channel_update
nvgpu_channel_update_gpfifo_get_and_get_free_count
nvgpu_channel_update_priv_cmd_q_and_free_entry
nvgpu_channel_wdt_continue
nvgpu_channel_wdt_handler
nvgpu_channel_wdt_init
nvgpu_channel_wdt_restart_all_channels
nvgpu_channel_wdt_restart_all_channels
nvgpu_channel_wdt_rewind
nvgpu_channel_wdt_start
nvgpu_channel_wdt_stop
nvgpu_channel_worker_deinit
nvgpu_channel_worker_from_worker
nvgpu_channel_worker_init
nvgpu_channel_worker_poll_init
nvgpu_channel_worker_poll_wakeup_post_process_item
nvgpu_channel_worker_poll_wakeup_process_item
nvgpu_submit_channel_gpfifo_kernel
nvgpu_submit_channel_gpfifo_user
gk20a_userd_gp_get
gk20a_userd_pb_get
gk20a_userd_gp_put
nvgpu_fence_alloc

The following members of struct nvgpu_channel are compiled out of
safety build.

struct gpfifo_desc gpfifo;
struct priv_cmd_queue priv_cmd_q;
struct nvgpu_channel_sync *sync;
struct nvgpu_list_node worker_item;
struct nvgpu_channel_wdt wdt;

The following files are compiled out of safety build.

common/fifo/submit.c
common/sync/channe1_sync_semaphore.c
hal/fifo/userd_gv11b.c

Jira NVGPU-3479

Change-Id: If46c936477c6698f4bec3cab93906aaacb0ceabf
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127212
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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2019-06-30 22:04:48 -07:00
Debarshi Dutta
f39a5c4ead gpu: nvgpu: rename gk20a_channel_* APIs
Renamed gk20a_channel_* APIs to nvgpu_channel_* APIs.
Removed unused channel API int gk20a_wait_channel_idle
Renamed nvgpu_channel_free_usermode_buffers in os/linux-channel.c to
nvgpu_os_channel_free_usermode_buffers to avoid conflicts with the API
with the same name in channel unit.

Jira NVGPU-3248

Change-Id: I21379bd79e64da7e987ddaf5d19ff3804348acca
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2121902
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2019-05-21 09:26:16 -07:00
Seema Khowala
c2b3da8e47 gpu: nvgpu: channel MISRA fix for Rule 17.7
Change gk20a_free_priv_cmdbuf from int to void type

Rename
gk20a_free_priv_cmdbuf -> nvgpu_channel_update_priv_cmd_q_and_free_entry
channel_gk20a_free_priv_cmdbuf -> nvgpu_channel_free_priv_cmd_q
free_priv_cmdbuf -> nvgpu_channel_free_priv_cmd_entry

JIRA NVGPU-3388
JIRA NVGPU-3248

Change-Id: I32bc5686a280f72c7bba4ab2d37782e29117f596
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114971
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
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2019-05-15 16:46:27 -07:00
Seema Khowala
671f1c8a36 gpu: nvgpu: channel MISRA fix for Rule 21.2
Rename
_gk20a_channel_get -> nvgpu_channel_get__func
gk20a_channel_get -> nvgpu_channel_get
_gk20a_channel_put -> nvgpu_channel_put__func
gk20a_channel_put -> nvgpu_channel_put
trace_gk20a_channel_get -> trace_nvgpu_channel_get
trace_gk20a_channel_put -> trace_nvgpu_channel_put

JIRA NVGPU-3388

Change-Id: I4e37adddbb5ce14aa18132722719ca2f73f1ba52
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114118
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2019-05-09 04:39:34 -07:00
Debarshi Dutta
17486ec1f6 gpu: nvgpu: rename tsg_gk20a and channel_gk20a structs
rename struct tsg_gk20a to struct nvgpu_tsg and rename struct
channel_gk20a to struct nvgpu_channel

Jira NVGPU-3248

Change-Id: I2a227347d249f9eea59223d82f09eae23dfc1306
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2112424
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2019-05-06 02:56:53 -07:00
Alex Waterman
6c2c4181ae gpu: nvgpu: Create hal.mm.mm for misc MM HALs
There are many miscellaneous HALs for various MM related functionality.
This patch aims to migrate all the remaining MM code from the <chip>/
mm_<chip>.[ch] files in HAL files under hal/.

Much of this is fairly straightforward copy/paste and updates to the
HAL init files.

The exception to that is the move of the left over gv11b MMU fault
handling code in mm_gv11b.c. Having both a hal/mm/mm/mm_gv11b.c and
a gv11b/mm_gv11b.c file causes tmake to choke so the gv11b/mm_gv11b.c
file was moved to gv11b/mmu_fault_gv11b.c. This will be cleaned up in
a subsequent patch.

JIRA NVGPU-2042

Change-Id: I12896de865d890a61afbcb71159cff486119ffb8
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109050
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2019-05-01 15:06:57 -07:00
Thomas Fleury
c270bb73ae gpu: nvgpu: rename syncpt and sema HALs
Renamed the following HALs
- syncpt.alloc_syncpt_buf -> syncpt.alloc_buf
- syncpt.free_syncpt_buf -> syncpt.free_buf
- syncpt.add_syncpt_wait_cmd -> syncpt.add_wait_cmd
- syncpt.get_syncpt_wait_cmd_size -> syncpt.get_wait_cmd_size
- syncpt.get_syncpt_incr_per_release -> syncpt.get_incr_per_release
- syncpt.add_syncpt_incr_cmd -> syncpt.add_incr_cmd
- syncpt.get_syncpt_incr_cmd_size -> syncpt.get_incr_cmd_size
- syncpt.get_sync_ro_map -> syncpt.get_sync_ro_map
- sema.get_sema_wait_cmd_size -> sema.get_wait_cmd_size
- sema.get_sema_incr_cmd_size -> sema.get_incr_cmd_size
- sema.add_sema_cmd -> sema.add_cmd

Renamed HAL implementations as:
- gk20a_alloc_syncpt_buf -> gk20a_syncpt_alloc_buf
- gk20a_free_syncpt_buf -> gk20a_syncpt_free_buf
- gk20a_add_syncpt_wait_cmd -> gk20a_syncpt_add_wait_cmd
- gk20a_get_syncpt_wait_cmd_size -> gk20a_syncpt_get_wait_cmd_size
- gk20a_get_syncpt_incr_per_release -> gk20a_syncpt_get_incr_per_release
- gk20a_add_syncpt_incr_cmd -> gk20a_syncpt_add_incr_cmd
- gk20a_get_syncpt_incr_cmd_size -> gk20a_syncpt_get_incr_cmd_size
- gv11b_alloc_syncpt_buf -> gv11b_syncpt_alloc_buf
- gv11b_free_syncpt_buf -> gv11b_syncpt_free_buf
- gv11b_add_syncpt_wait_cmd -> gv11b_syncpt_add_wait_cmd
- gv11b_get_syncpt_wait_cmd_size -> gv11b_syncpt_get_wait_cmd_size
- gv11b_add_syncpt_incr_cmd -> gv11b_syncpt_add_incr_cmd
- gv11b_get_syncpt_incr_cmd_size -> gv11b_syncpt_get_incr_cmd_size
- gv11b_get_syncpt_incr_per_release -> gv11b_syncpt_get_incr_per_release
- gv11b_get_sync_ro_map -> gv11b_syncpt_get_sync_ro_map
- gk20a_get_sema_wait_cmd_size -> gk20a_sema_get_wait_cmd_size
- gk20a_get_sema_incr_cmd_size -> gk20a_sema_get_incr_cmd_size
- gk20a_add_sema_cmd -> gk20a_sema_add_cmd
- gv11b_get_sema_wait_cmd_size -> gv11b_sema_get_wait_cmd_size
- gv11b_get_sema_incr_cmd_size -> gv11b_sema_get_incr_cmd_size
- gv11b_add_sema_cmd -> gv11b_sema_add_cmd

Jira NVGPU-1984
Jira NVGPU-1986

Change-Id: I3eb3f669093588df422a82c54fa1ca64788a490c
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2096374
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2019-04-16 10:46:32 -07:00
Thomas Fleury
656a9aa170 gpu: nvgpu: split sync HAL into syncpt and sema
Split sync HAL into sync.syncpt and sync.sema

Jira NVGPU-1984
Jira NVGPU-1986

Change-Id: I66bd6948e1d77b7728a667de3d3b1ae2adc62e27
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2096373
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2019-04-16 10:46:17 -07:00
Seema Khowala
312f91f991 gpu: nvgpu: move fence_gk20a to common/fence
Move gk20a/fence_gk20a.c to common/fence/fence.c

Renamed
gk20a_fence_from_semaphore -> nvgpu_fence_from_semaphore
gk20a_fence_from_syncpt -> nvgpu_fence_from_syncpt
gk20a_alloc_fence_pool -> nvgpu_fence_pool_alloc
gk20a_free_fence_pool -> nvgpu_fence_pool_free
gk20a_alloc_fence -> nvgpu_fence_alloc
gk20a_init_fence -> nvgpu_fence_init
gk20a_fence_put -> nvgpu_fence_put
gk20a_fence_get -> nvgpu_fence_get
gk20a_fence_wait -> nvgpu_fence_wait
gk20a_fence_is_expired -> nvgpu_fence_is_expired
gk20a_fence_install_fd -> nvgpu_fence_install_fd
gk20a_fence_ops struct -> nvgpu_fence_ops struct
gk20a_fence struct -> nvgpu_fence_type struct

JIRA NVGPU-1982

Change-Id: Ife77b2c3c386ff4368683c78ca02f00c99cddb4b
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2093002
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2019-04-10 17:24:52 -07:00
Philip Elcan
ab5684ce1b gpu: nvgpu: channel: use u32 for syncpt id
Make the APIs nvgpu_channel_sync_get_syncpt_id() and
channel_sync_syncpt_get_id() return u32s rather than converting to
ints and back.

Also define FIFO_INVAL_SYNCPT_ID to use for invalid syncpt IDs rather
than using magic numbers.

JIRA NVGPU-1008

Change-Id: I4dde6b15fd3708fb0126b46c6fea8ac1b447c7ce
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2014821
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2019-02-11 12:55:36 -08:00
Debarshi Dutta
8b57b3b938 gpu: nvgpu: restructure sync cmdbufs specific gpu_ops
sync cmbbuf specific ops pointers are moved into a new struct sync_ops
under the parent struct gpu_ops. The HAL assignments to the gk20a and
gv11b versions are updated to match the new struct type.

Jira NVGPU-1308

Change-Id: I1d9832ed5e938cb65747f0f6d34088552f75e2bc
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1975919
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2019-01-25 02:45:11 -08:00
Scott Long
6b66428a34 gpu: nvgpu: container_of() changes to ch sync code
The container_of() macro used in nvgpu produces the following set
of MISRA required rule violations:

 * Rule 11.3 : A cast shall not be performed between a pointer to
               object type and a pointer to a different object to type.

 * Rule 11.8 : A cast shall not remove any const or volatile
               qualification from the type pointed to be a pointer.

 * Rule 20.7 : Expressions resulting from the expansion of macro
               parameters shall be enclosed in parentheses.

Using the same modified implementation of container_of() as that
used in the nvgpu_list_node/nvgpu_rbtree_node routines eliminates
the Rule 11.8 and Rule 20.7 violations and exchanges the Rule 11.3
violation with an advisory Rule 11.4 violation.

This patch uses that same equivalent implementation in two new
(static) functions that are used to replace references to
container_of() in common channel sync code:

 * nvgpu_channel_sync_semaphore_from_ops
 * nvgpu_channel_sync_syncpt_from_ops

It should be noted that replacement functions still contain
potentially dangerous (and non-MISRA compliant code) and that it is
expected that deviation requests will be filed for the new advisory
rule violations accordingly.

JIRA NVGPU-782

Change-Id: Ib4279c7d28824ce5888838580a54b573323f7152
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1993787
Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2019-01-15 14:03:50 -08:00
Debarshi Dutta
6fe9bb835b gpu: nvgpu: access channel_sync via public API
struct nvgpu_channel_sync is moved to a private header i.e.
channel_sync_priv.h present in common/sync/. All accesses to callback
functions inside the struct nvgpu_channel_sync in NVGPU driver is replaced by
the public channel_sync specific APIs.

Jira NVGPU-1093

Change-Id: I52d57b3d458993203a3ac6b160fb569effbe5a66
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1929783
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2018-10-26 02:12:23 -07:00
Debarshi Dutta
715d35e137 gpu: nvgpu: separate syncpoint function definitions to separate unit
Add the following syncpt specific APIs

nvgpu_channel_sync_get_syncpt_id
nvgpu_channel_sync_get_syncpt_address
nvgpu_channel_sync_wait_syncpt
nvgpu_channel_sync_to_syncpt
nvgpu_channel_sync_syncpt_create

Definition of struct nvgpu_channel_sync_syncpt and syncpoint
specific static implementations of the channel_sync callbacks
as well as definitions of the public APIs are moved to a
separate execution unit i.e. channel_sync_syncpt.c

Jira NVGPU-1093

Change-Id: Ib0163c6b9bc6dfc2ab2a2b7a5fa5027be13316e2
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1929780
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2018-10-26 02:12:05 -07:00