Request irq at probe instead of at poweron. This allows investigating
interrupt numbers across rail gating cycles.
Change-Id: I6db4b3f1d865c6fbbd9d6a96c3df89617e169891
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/374859
Interrupts may be needed before we have actually silenced all
channels. Few possible scenarios include channel recovery during
teardown and sw method before the channels have been suspended.
This patch modifies the teardown path so that we disable interrupts
after the channels have been suspended.
Change-Id: Ifc36dbb74b1d36bd88d1220fa50a53c4072df4d8
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/394599
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Result of top_fs_status_r() is always constant. Do not dump it
anymore.
Change-Id: Ie1cfe872d70b2c3c8a7cef4df3870dacae8f8793
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/395208
Ensure devfreq is disabled before shutting down gk20a, to prevent
possible races with reading of gpu load, and the shutdown of gpu itself.
Bug 1492913
Change-Id: I016fdba9515120fc6cf3e771f60c61b9bf2027cb
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/394296
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Free IRQs before the various subunits are suspended. This is to prevent
potential races between the IRQ thread and the suspend routine.
Bug 1437749
Change-Id: Iffef918feecae0b256be96efd02b01b2677c225d
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
This patch adds a field to the gpu capability ioctl to allow
requesting the maximum VA a single PDE entry can hold.
Bug 1456570
Change-Id: I5cf29c8816fa6ea396c36419e6821c27a805b8af
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
