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13 Commits

Author SHA1 Message Date
Thomas Fleury
7eb8ea9764 gpu: nvgpu: unit: add tsg abort coverage 
Add unit test for:
- nvgpu_tsg_abort

Jira NVGPU-3476

Change-Id: Ie1d93647e8ab239ad0604b04a3d36464b2bedb5b
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2124515
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-07 03:27:32 -07:00
Thomas Fleury
2b3f005313 gpu: nvgpu: unit: add tsg unbind branch coverage 
Updated test to cover test where:
- update runlist fails during unbind
- tsg is aborted
- updated runlist fails during abort

Modified update runlist stub to return -EINVAL depending
on branch combinations.

Added custom pruning function to skip some impossible
combinations of non-final branches.

Jira NVGPU-3476

Change-Id: I23a64085239b4003b73873a984a301476d73d962
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2124513
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-07 03:27:23 -07:00
Thomas Fleury
32aa15f9d4 gpu: nvgpu: unit: add tsg enable/disable coverage 
Add unit tests for
- g->ops.tsg.enable (gv11b_tsg_enable)
- g->ops.tsg_disable (nvgpu_tsg_disable)

Use an array to allow multiple stubs to store data.

Jira NVGPU-3476

Change-Id: I2afaef6d1ec4d74a05ec6e7952e5ead86c432f3d
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2123886
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-07 03:27:13 -07:00
Thomas Fleury
04cf2f1ba6 gpu: nvgpu: unit: add unit_assert helper 
Add unit_assert helper to check condition.
In case of failure, the macro reports failed condition as well as
line number, then runs bail out code.

Jira NVGPU-3476

Change-Id: I9971e7fa0337661d46a06dfa05b67a98e3c46eee
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2129675
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-07 03:27:04 -07:00
Thomas Fleury
eb380fcbdb gpu: nvgpu: unit: tmake userspace build for tsg 
Added tmake userspace build for tsg
Added missing exports for libnvgpu-drv
Added tsg tests to required tests
Re-use fifo init/remove support

Jira NVGPU-3476

Change-Id: I5bcbbf5a9b58e825e1cad6aa5896de7e91fe7400
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128160
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-07 03:26:54 -07:00
Thomas Fleury
c6d51b20d5 gpu: nvgpu: unit: add unbind channel check_ctx_reload 
Add test for nvgpu_tsg_unbind_channel_check_ctx_reload.
Check that force reload is done for other channel in TSG.

Jira NVGPU-3476

Change-Id: I1889442f81f2373127cc6db173a64eff6a07a981
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2123884
GVS: Gerrit_Virtual_Submit
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-31 11:16:22 -07:00
Thomas Fleury
53b82d5a84 gpu: nvgpu: unit: add unbind channel check_hw_state 
Add coverage for nvgpu_tsg_unbind_channel_check_hw_state.

Jira NVGPU-3476

Change-Id: Ie1fcea234bb234a757ce4cc3b21d51b7b13c4d03
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2123883
GVS: Gerrit_Virtual_Submit
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-31 11:16:12 -07:00
Thomas Fleury
4fad611cb9 gpu: nvgpu: unit: add tsg bind/unbind coverage 
Add coverage for
- nvgpu_tsg_bind_channel
- nvgpu_tsg_unbind_channel

Added pruning mechanism to skip subtests that attempt to test
some branches after a final branch.

Jira NVGPU-3476

Change-Id: I8e9a865055f36bc237a510ff93ab5385d430f5d1
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2121251
GVS: Gerrit_Virtual_Submit
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-31 11:16:03 -07:00
Thomas Fleury
29fc98550b gpu: nvgpu: unit: add tsg open/release coverage 
Added coverage for
- nvgpu_tsg_open
- nvgpu_tsg_release

In order to cover branch combinatorial, a bitmask is used.
For each branch, one bit indicates if the branch is taken or not.
A loop calls the tested function with all combinations.
We could afterwards prune some combinations for branches that
directly exit the function.

Set MM_UNIFIED_MEMORY feature to avoid allocating from vidmem.

Jira NVGPU-3476

Change-Id: If2e82eabfa492b4c9ec727e175f31b53fbb4f5f1
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2123156
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-31 11:15:53 -07:00
Thomas Fleury
0a2bac5974 gpu: nvgpu: unit: add io callbacks for tegra fuses 
Remove WAR to set FMODEL during gv11b_init_hal.
Instead, add io callbacks for tegra fuses, and return
GCPLEX_CONFIG_WPR_ENABLED_MASK for FUSE_GCPLEX_CONFIG_FUSE_0.

Jira NVGPU-3476

Change-Id: I0739d66668b0f5c6658346b67bc368682edda4da
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120680
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-24 19:05:47 -07:00
Thomas Fleury
20d611b081 gpu: nvgpu: unit: move gv11b reg spaces to unit/fifo 
Move gv11b reg spaces initializations to unit/fifo, so that
it can be re-used by all fifo sub-units.

Jira NVGPU-3476

Change-Id: I9dd8564e71cb1b4c90a6a7df856e6eeadfedc649
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120585
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-24 19:05:11 -07:00
Thomas Fleury
1456c788f3 gpu: nvgpu: unit: stub userd.setup_sw 
Regular USERD init requires bar1.vm to be initialized
Use a stub in unit tests, since it will be disabled in
safety build anyway.

Jira NVGPU-3476

Change-Id: I9bc3ab8ca1ab578a90dbc66167ee535046faae92
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2122297
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-21 10:36:37 -07:00
Thomas Fleury
e140d72ff8 gpu: nvgpu: unit: add tests for common.fifo.tsg 
Added pre-populated register spaces for gv11b:
- NV_PFIFO 0x00003FFF:0x00002000
- NV_PTOP 0x000227FF:0x00022400

Registers values were captured on DDPX with reg_dump,
after disabling railgating and ELPG.

This allows running nvgpu_fifo_init_support, using
gv11b HALs.

Added the following tests:
- test_fifo_init_support
- test_tsg_open
- test_tsg_release
- test_fifo_remove_support

Jira NVGPU-3476

Change-Id: Ia717d9a9d431248635d51d0c265c16c2b6806a95
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120564
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-17 10:46:09 -07:00