When reviewing some VM mapping code I found the name of the function
that actually maps the passed buffer to be confusing. It was:
nvgpu_vm_map_compression_comptags()
This function does actually do the map and work out some comptags
related stuff. But I think this would be easier to read in the code
as:
nvgpu_vm_do_map()
As this is much more literally what the function is actually doing.
Change-Id: I9a945b198887f5fb23b8be622c8411f97358dbed
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2220339
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The init unit test starts the quiesce feature during testing. This
includes starting the quiesce thread. The thread should be stopped when
the init unit tests complete, so call nvgpu_sw_quiesce_remove_support()
when complete.
Bug 2732985
Change-Id: I701e1dd1ce753781fa81327e3cdc7e2881a33d00
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2224307
Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
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Functions for copying to falcon memory typecast from pointer to char of
input buffer to pointer to u32 since falcon data registers are written
in 4-bytes. Firmware data is generally byte stream and hence we won't
be able to deal with input buffer as pointer to u32.
Hence, misra rule 11.3 deviation is required for these casts. Firmware
data is also not aligned at word boundary sometimes hence we need to
copy it to aligned buffer to conform to the deviation recommendation.
hal/falcon/falcon_gk20a_fusa.c:136
Checker: MISRA C-2012 Rule 11.3 (Required)
misra_c_2012_rule_11_3_violation: The object pointer expression "src"
of type "u8 *" is cast to type "u32 *".
This patch implements copy to falcon memory from unaligned source byte
by byte and casts the input buffer to u32 pointer otherwise.
JIRA NVGPU-4128
Change-Id: Iff3cc1010b8e209ec453c10c6d46953cf5a8adbe
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2210321
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Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
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Move ptimer unit HALS outside gk20a.h. This is required for
documenting the HALs. We divide the ptimer unit HALs into 3 categories:
1. Private HALs
2. FUSA HALs
3. NON-FUSA HALs
This classification will help focus only on FUSA HALs in design
document and exclude the non-safety related ones from design
document.
Add ptimer HAL header file which contains the HALs exposed by ptimer
unit.
Use @cond...@endcond to skip documentation for NON-FUSA HALs and
private HALs from ptimer unit.
Add doxygen comments for
1. ptimer unit's public HAL used in safety build
a. ptimer.isr
2. ptimer unit's public APIs
a. ptimer_scalingfactor10x()
b. ptimer_scale()
JIRA NVGPU-2503
Change-Id: If5fb00733e122b27826ec36503f175fae172c71b
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2219427
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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In the change_seq of latest ucode, the boot pstate
index was taken from pstate board_objs instead of the
value from change_input. This forces the need of
introducing boot index in pstate board_obj structure.
The index is the performance table entry index of
P0 pstate.
The ucode change is described in P4CL #27304645
NVGPU-4081
Change-Id: Id3f4a1da7015cd6b7efe555529f1fa13c9f3b391
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2202363
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Currently nvgpu reads the temperature by reading the
NV_THERM_I2CS_SENSOR_00 register. Below are the issues
with current approach
1) NV_THERM_I2CS_SENSOR_00 doesn't support
fractional precision which is POR.
2) It doesn't support negative temperatures which
is required for Auto.
3) It doesn't take into account the right POR
sensor in VFE VBIOS tables.
From therm channel get status interface we can read the
current temperature from PMU.
NVBUG - 200549047
Change-Id: I2fb21926208876f3d3bebe3f2dee08edafedbc7d
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2196224
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This patch brings a number of changes to the mm.vm unit test:
- test_map_buf: add steps to check for error cases and increase
coverage.
- test_map_buf_gpu_va: add steps to check for error cases and
increase coverage.
- test_init_error_paths: new test to target all possible error
paths in the VM init code.
- test_map_buffer_error_cases: new test to target all possible
error paths in the buffer mapping logic.
- test_nvgpu_vm_alloc_va: new test to target the nvgpu_vm_alloc_va
API and also target error paths.
- test_vm_bind: new test to target the nvgpu_vm_bind_channel API
and also target error paths.
- test_vm_aspace_id: new test to target the vm_aspace_id API
and also target error paths.
JIRA NVGPU-909
Change-Id: I755c89a6de09376d2624130a98966c172d850bfe
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
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There are 2 instances where some code is unreachable in vm.c
- The nvgpu_insert_mapped_buf function always returned 0, so any
associated error handling was unreachable. This patch changes
the function to return void instead.
- A cleanup section to unmap a buffer in case of error was also
unreachable.
JIRA NVGPU-909
Change-Id: I6d8343b2994d314992a61dd640b10e68fbbc5e1e
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2217677
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Update struct nvgpu_fecs_ecc_status comments for doxygen.
Move structures for method, mailbox and cond outside
the nvgpu_fecs_method_op struct, for better doxygen
format. Defining sturct within struct doesnot look
good in doxygen.
Jira NVGPU-4107
Change-Id: I34b2249119e5578c568139f958e6edab9d75d7c8
Signed-off-by: Vinod G <vinodg@nvidia.com>
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This move is required for documenting the HALs. We divide the
Top unit HALs into 3 categories:
1. Private HALs
2. FUSA HALs
3. NON-FUSA HALs
This classification will help focus only on FUSA HALs in design
document and exclude the non-safety related ones from design
document.
Also, add this HAL header file to yaml.
JIRA NVGPU-2500
Change-Id: I8325b4bb2677cba9be94e15ec2683d1c9e0bc68e
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2215228
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Add more doxygen to common members of struct gk20a. Use @cond/@endcond
to limit inclusion of non-FUSA members. There's a number of
unit-specific members that are still undocumented.
JIRA NVGPU-2532
Change-Id: Ie0cb419e620b08405f9ed5890c712a937eb5c88d
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2220456
Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Update defaults header to include doxygen documentation
for various default values used in NvGPU.
Currently, the header defines default values only for
timeouts.
JIRA NVGPU-2418
Change-Id: I4a29024dc6bf19c32a5070d0d75aa84ddebc3379
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2219271
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