Sagar Kamble
a776f7b1d9
gpu: nvgpu: make global allowlist and range arrays static const
...
Allowlist and register ranges are declared global. Sparse throws warning
for them as:
- allowlist_ga100.c:351:5: warning: symbol
'ga100_cau_register_offset_allowlist' was not declared.
Should it be static?
- allowlist_ga100.c:389:47: warning: symbol
'ga100_hwpm_pma_trigger_register_ranges' was not declared.
Should it be static?
Make these arrays static global const.
Bug 3528472skamble@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2676591
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2022-03-03 01:41:25 -08:00
Antony Clince Alex
6bfa11c327
gpu: nvgpu: ga10b: update regops allowlist
...
Update regops allowlist using the latest hw headers.
Bug 3455929
Jira NVGPU-7365
Change-Id: I4f866b81de2a7d689f1b633a498a8c0c9a26a226
Signed-off-by: Antony Clince Alex <aalex@nvidia.com >
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2022-01-17 05:35:57 -08:00
Antony Clince Alex
bf5f789805
gpu: nvgpu: gv11b: update regops allowlist
...
Update regops allowlist to include perfmon register
NV_PERF_PMM_CLAMP_CYA_CONTROL(i).
Bug 200780938
Change-Id: I9f3644d327ca054d455c34fd4daa7b8d352d6616
Signed-off-by: Antony Clince Alex <aalex@nvidia.com >
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2021-12-03 08:44:02 -08:00
Tejal Kudav
3b1bbc7259
gpu: nvgpu: Remove GP10b support
...
Starting 6.0.2.0, deprecate support for GP10b. Delete GP10b specific
things such as platform data, ucodes, regops allowlist, cg/pg register
list. Per unit specific gp10b code cleanup will be done later.
Bug 3431142
Change-Id: I4d5fd9ad8c6ee53845df3b6b2298af64d76e86c3
Signed-off-by: Tejal Kudav <tkudav@nvidia.com >
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2021-12-03 08:43:52 -08:00
Sagar Kadamati
3e43f92f21
gpu: nvgpu: add ga10b & ga100 sources
...
Mass copy ga10b & ga100 sources from nvgpu-next repo.
TOP COMMIT-ID: 98f530e6924c844a1bf46816933a7fe015f3cce1
Jira NVGPU-4771
Change-Id: Ibf7102e9208133f8ef3bd3a98381138d5396d831
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2524817
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2021-06-17 12:56:16 -07:00
Deepak Nibade
fae1f20ab7
gpu: nvgpu: update tu104 regops allowlist
...
Sync tu104 regops allowlist to latest allowed values.
Bug 200605637
Change-Id: I6287cf4deb74418d5d25aef5a19259cc4813c80c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2476116
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2021-01-29 08:00:46 -08:00
Mayur Poojary
160c6c16bd
gpu: nvgpu: Add auto-generated regops allowlist
...
Add auto-generated regops allowlist files for gv11b and tu104.
Update Makefiles accordingly.
Bug 2510974
Bug 200668999
Jira NVGPU-5360
Change-Id: I5bc6a220ef6f90838e0ba735b1ee8e97d8f9215f
Signed-off-by: Mayur Poojary <mpoojary@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2423637
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2020-12-15 14:13:48 -06:00
Deepak Nibade
1ff79b1d2c
gpu: nvgpu: remove support for quad reg_op
...
quad type reg_ops were only needed on Kepler, and not for any other chip
beginning Maxweel.
HAL g->ops.gr.access_smpc_reg() was incorrectly set for Volta and Turing
whereas it was only applicable to Kepler. Delete it.
There is no register in the quad type whitelist since the type itself is
not supported anymore. Remove the empty whitelists for all chips and
also delete below HALs:
g->ops.regops.get_qctl_whitelist()
g->ops.regops.get_qctl_whitelist_count()
hal/regops/regops_gv100.* files are not used anymore. Delete the files
instead of just deleting quad HALs in these files.
Bug 200628391
Change-Id: I4dcc04bef5c24eb4d63d913f492a8c00543163a2
Signed-off-by: Deepak Nibade <dnibade@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2366035
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2020-12-15 14:13:28 -06:00
Deepak Nibade
67350e2c9c
gpu: nvgpu: add flags to debugger specific headers
...
Add debugger/cyclestats/fecs_trace compile time flags to debugger
specific unit headers
Jira NVGPU-3506
Change-Id: Iedea5f274243a389dce91edecbc80c58753d4805
Signed-off-by: Deepak Nibade <dnibade@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2137253
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2019-06-18 01:38:54 -07:00
Deepak Nibade
840972c1cc
gpu: nvgpu: update TU104 regops whitelist
...
List of whitelisted registers is auto generated with script
Bug 200526741
Change-Id: I097f4638ce9c1498ae09cfea2dbc7386fc5e0004
Signed-off-by: Deepak Nibade <dnibade@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2135669
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2019-06-13 09:35:55 -07:00
Deepak Nibade
88c8baa29f
gpu: nvgpu: create common.hal.regops unit
...
Create common.hal.regops unit by moving all regops chip files under
hal/ directory
Update Makefiles and include paths accordingly
Jira NVGPU-2037
Change-Id: Iac1833b8916d919f7d448d17f5dd7a853760f55c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com >
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2019-04-12 04:05:04 -07:00
