- Remove non-safe TPC powergate feature from the safety
build by introducing a new flag:
CONFIG_NVGPU_TPC_POWERGATE
- Move nvgpu_init_power_gate_gr() under same compile time flag.
and move HAL function gr_gv11b_powergate_tpc() to tpc_gv11b.c
- Also, remove the negative test scenario and
usage of tpc_powergate from unit tests
JIRA NVGPU-4149
Change-Id: If489482401e94de499e472b16b1bc091b00992e6
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2242323
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Set the unit test configs correctly for the QNX unit test build.
The defines __NVGPU_UNIT_TEST__ and
NVGPU_UNITTEST_FAULT_INJECTION_ENABLEMENT were not being set for the
unit tests in the QNX build, only for the libnvgpu_ut.so. Therefore,
some structs were defined differently in the two files causing
segfaults.
JIRA NVGPU-3981
Change-Id: Ia4fbaae7df89b9034a3d50a8c99eefe1d19898a8
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2245554
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
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Previously, unit interrupt enabling/disabling and corresponding MC level
interrupt enabling/disabling was not done at the same time.
With this change, stall and nonstall interrupt for units are programmed
at MC level along with individual unit interrupts. Kept access to MC
interrupt registers through mc.intr_lock spinlock.
For doing this separated CE and GR interrupt mask functions.
mc.intr_enable is only used when there is global interrupt
control to be set. Removed mc_gp10b.c as mc_gp10b_intr_enable
is now removed. Removed following functions - mc_gv100_intr_enable,
mc_gv11b_intr_enable & intr_tu104_enable. Removed intr_pmu_unit_config
as we can use the generic unit interrupt control function.
JIRA NVGPU-4336
Change-Id: Ibd296d4a60fda6ba930f18f518ee56ab3f9dacad
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2196178
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To enable ecc interrupts early during nvgpu_finalize_poweron, ecc
support has to be enabled early. ecc support was being initialized
together for GR, LTC, PMU, FB units late in the poweron sequence.
Move the ecc init for each unit to respective unit's init functions.
And separate out the hal ecc functions from GR ecc unit to
respective hal units.
JIRA NVGPU-4336
Change-Id: I2c42fb6ba3192dece00be61411c64a56ce16740a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2239153
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Add tests to cover common.gr.setup subunit. This includes
g->ops.gr.setup.alloc_obj_ctx
g->ops.gr.setup.set_preemption_mode
g->ops.gr.setup.free_gr_ctx and
g->ops.gr.setup.free_subctx.
Update register space to include the registers used by
context creation.
Update SWUT files for doxygen.
Jira NVGPU-3968
Change-Id: I3ab539d18584231142a1945d621d015b7ca772de
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2244825
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Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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Provide test_gr_init_setup_ready function which cover the
test_gr_init_setup, test_gr_init_prepare and test_gr_init_support
calls needed for each gr sub-units.
test_gr_setup_cleanup function which cover the
test_gr_remove_support and test_gr_remove_setup calls.
Update gr.intr and gr.falcon subunit tests to use these functions.
Jira NVGPU-3968
Change-Id: I90c890dc9802b59f60d8f2db436491acba313398
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2242861
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This function gets the GPU chip architecture, implementation and
revision information by reading the MC boot register, hence it
is more suited to be located in HAL files.
test_check_gpu_state is now being run after test_hal_init as the
gops.mc needs to be initialized for test_check_gpu_state subtest.
JIRA NVGPU-2524
Change-Id: I85355af11d3505a9eb4f10a3fe4e6d9b56285047
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2226018
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gk20a.h will include gops_mc.h to contain the mc ops definitions. Add
doxygen comments for the HAL functions that are called directly.
Also move mc_gp10b_intr_pmu_unit_config to non-fusa HAL file.
JIRA NVGPU-2524
Change-Id: I4f326332d7842211b004b372d79fac9fe6ed40e7
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2226017
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The two MM functions nvgpu_set_pd_level() and nvgpu_vm_do_free_entries()
are simple recursive functions for processing page descriptors (PDs) by
traversing the levels in the PDs. MISRA Rule 17.2 prohibits functions
calling themselves because "unless recursion is tightly controlled, it
is not possible to determine before execution what the worst-case stack
usage could be." So, this change limits the recursion depth of each of
these functions to the maximum number of page table levels by checking
the level against the MM HAL max_page_table_levels().
This also required configuring this HAL in various unit tests as they
were no previously using this HAL.
JIRA NVGPU-3489
Change-Id: Iadee3fa5ba9f45cd643ac6c202e9296d75d51880
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2224450
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nvgpu_falcon_setup_bootstrap_config functionality can be kept static.
nvgpu_falcon_bl_bootstrap and nvgpu_falcon_bl_info are removed as it
is replaced by nvgpu_falcon_hs_ucode_load_bootstrap.
Update the test case accordingly, SWUTS and doxygen comments. Other
nits addressed about doxygen documentation.
JIRA NVGPU-2412
Change-Id: Idaa670ce6d6d6b735b4a2af34e1f1a229ff2a3e9
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2220089
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
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The init unit test starts the quiesce feature during testing. This
includes starting the quiesce thread. The thread should be stopped when
the init unit tests complete, so call nvgpu_sw_quiesce_remove_support()
when complete.
Bug 2732985
Change-Id: I701e1dd1ce753781fa81327e3cdc7e2881a33d00
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2224307
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
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This patch brings a number of changes to the mm.vm unit test:
- test_map_buf: add steps to check for error cases and increase
coverage.
- test_map_buf_gpu_va: add steps to check for error cases and
increase coverage.
- test_init_error_paths: new test to target all possible error
paths in the VM init code.
- test_map_buffer_error_cases: new test to target all possible
error paths in the buffer mapping logic.
- test_nvgpu_vm_alloc_va: new test to target the nvgpu_vm_alloc_va
API and also target error paths.
- test_vm_bind: new test to target the nvgpu_vm_bind_channel API
and also target error paths.
- test_vm_aspace_id: new test to target the vm_aspace_id API
and also target error paths.
JIRA NVGPU-909
Change-Id: I755c89a6de09376d2624130a98966c172d850bfe
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2217679
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-Renamed ACR structs for FUSA, ACR FUSA code has struct names
ending with _v1 & ACR non-FUSA with _v0, removed _v1 for FUSA
code to keep struct without any versioning for doxygen.
-Renamed acr_blob_construct_v1.c/h to acr_blob_construct.c/h
JIRA NVGPU-2516
Change-Id: Id2d5e48e8169ce59371c2b08d04c5a65ba94c685
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2218265
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Add support for interrupt unit tests for following use cases
1. with channel and without tsg.
2. with channel and tsg, without setting the context to local cache.
3. with channel and tsg, setting the context to local cache
Jira NVGPU-4096
Change-Id: Ib9e5b49f5c5b94d785b9e225a84f3b2829fd3cf7
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2213089
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IRQs can get triggered during nvgpu power-on due to MMU fault, invalid
PRIV ring or bus access etc. Handlers for those IRQs can't access the
full state related to the IRQ unless nvgpu is fully powered on.
In order to let the IRQ handlers know about the nvgpu power-on state
gk20a.power_on_state variable has to be protected through spinlock
to avoid the deadlock due to usage of earlier power_lock mutex.
Further the IRQs need to be disabled on local CPU while updating the
power state variable hence use spin_lock_irqsave and spin_unlock_-
irqrestore APIs for protecting the access.
JIRA NVGPU-1592
Change-Id: If5d1b5e2617ad90a68faa56ff47f62bb3f0b232b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2203860
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Add unit tests for:
- gv11b_tsg_init_eng_method_buffers
- gv11b_tsg_deinit_eng_method_buffers
- gv11b_tsg_bind_channel_eng_method_buffers
- gv11b_tsg_unbind_channel_check_eng_faulted
Note: gv11b_tsg_enable was already tested as part of TSG common.
Added SWUTS documentation for above tests.
Modified gv11b_tsg_init_eng_method_buffers to inline computation
of method buffer size, as existing static function could never
return 0, making one branch not testable.
Added dummy IO register spaces for PFB, CE, PBUS and HSUB_COMMON,
so that g->ops.mm.init_mm_support can be called as part of
test_fifo_init_support. MM support is needed to test allocation
and mapping of DMA buffers.
Jira NVGPU-3788
Change-Id: I5356531b23c0456662187d16b35955bf0e528782
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2207384
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