3 Commits

Author	SHA1	Message	Date
Vedashree Vidwans	cd7194cbc0	gpu: nvgpu: modify gmmu page table entry functions ... Move below chip agnostic gmmu pte functions to common/mm/gmmu/pte.c. - gmmu_aperture_mask() - pte_dbg_print() Default big page size for all chips is 64K. So, move gp10b_mm_get_default_big_page_size() to common file and rename as nvgpu_gmmu_default_big_page_size(). Modify gv11b_gpu_phys_addr() to use get_iommu_bit() hal. JIRA NVGPU-4666 Change-Id: I512c42723faf2d03e5b367879c9c385dcf52cdc2 Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2329560 Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2020-12-15 14:13:28 -06:00
Vedashree Vidwans	afae2efc23	gpu: nvgpu: fix MISRA errors in nvgpu.hal.mm ... Rule 8.6 requires each identifier with external linkage to have exactly one external definitions. Rule 10.x necessitates operands to have essential type; left and right operands should be of same width and type. Rule 14.3 doesn't allow controlling expressions to be invariant; ensuring that all conditions are possible. Jira NVGPU-3858 Change-Id: I043a3836c4a2cb9c5a52d3053516c517389f55a2 Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2162295 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-07-29 12:45:40 -07:00
Alex Waterman	00d7b53b73	gpu: nvgpu: Move remaining GMMU HAL code to hal/mm/gmmu/ ... Move the remaining GMMU HAL related code from the gm20b/, gp10b/, and gv11b/ directories to new gmmu hal source files. Also update all makefiles and HAL init code to refelct the new location of the headers and source code. JIRA NVGPU-2042 Change-Id: Ic9b85cc547bd0f994ad11042fc4093c517327399 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2103672 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-04-26 09:36:26 -07:00