3 Commits

Author	SHA1	Message	Date
Seema Khowala	dfafddcc21	gpu: nvgpu: move common and chip specific ctxsw timeout ... Delete apply_ctxsw_timeout_intr ops and add ctxsw_timeout_enable ops Move chip specific sched_error and ctxsw_timeout functions to hal/fifo/fifo_intr_* and hal/fifo/ctxsw_timeout_* Add nvgpu_rc_ctxsw_timeout function under common/rc/rc.c Do not check ctxsw timeout for channels that are no more bound to tsg. JIRA NVGPU-1312 Change-Id: Ide977fb60b3b72a27d9f22873f7a416c3bd1181d Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2075734 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-03-25 22:47:45 -07:00
Seema Khowala	fe2a599700	gpu: nvgpu: rename fifo_eng_timeout_us ... Rename fifo_eng_timeout_us to ctxsw_timeout_period_ms for clarity. JIRA NVGPU-1312 Change-Id: I23faff3df7160c1193f797ac03769ef2ecf4449e Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2076776 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-03-25 22:47:09 -07:00
Seema Khowala	f66f3e1341	gpu: nvgpu: move fifo intr to hal/fifo ... Removed intr_0_error_mask ops Added below ops for fifo intr intr_0_enable intr_1_enable intr_0_isr intr_1_isr JIRA NVGPU-1310 Change-Id: I19bd1a380a89cffd582d6c4a0b7796a46fec5afb Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2072144 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-03-25 11:03:39 -07:00