Commit Graph

15 Commits

Author SHA1 Message Date
Terje Bergstrom
e2638d73fd gpu: nvgpu: Wait for idle via FIFO registers
Wait for engine idle via FIFO's engine status instead of submitting
WFI to channel. Submitting WFI and waiting is not robust, and wait
might invoke debug dump which cannot be done while powering down.

Bug 1499214

Change-Id: I4d52e8558e1a862ad4292036594d81ebfbd5f36b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/432151
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Sachin Nikam <snikam@nvidia.com>
2015-03-18 12:10:20 -07:00
Deepak Nibade
b6466fbe07 gpu: nvgpu: add TSG support to runlists
- when a TSG channel is made runnable, add it to TSG's
  runnable list
- when a TSG channel is removed from runlist, remove it
  from TSG's runnable list

When we rewrite the entire runlist :
- first add all the channels which are not part of any TSG
- then find all active TSGs, add an entry in runlist for the TSG
  (with TSG id and length of TSG)
- then write entries for each channel in that TSG

Bug 1470692

Change-Id: Ic55a4d5959abc72cd20b8224eb4c31d3ff411861
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/416612
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:10:16 -07:00
Deepak Nibade
e6eb4b59f6 gpu: nvgpu: add kernel APIs for TSG support
Add support to create/destroy TSGs using node "/dev/nvhost-tsg-gpu"

Provide below IOCTLs to bind/unbind channels to/from TSGs :

NVGPU_TSG_IOCTL_BIND_CHANNEL
NVGPU_TSG_IOCTL_UNBIND_CHANNEL

Bug 1470692

Change-Id: Iaf9f16a522379eb943906624548f8d28fc6d4486
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/416610
2015-03-18 12:10:16 -07:00
Terje Bergstrom
c32ac10b0b gpu: nvgpu: Dump offending push buffer fragment
When outputting debug dump, print the contents of current push buffer
segment.

Also changes the debug dump to use pr_cont when applicable, and dumps
state before recovering in case channel was not loaded to an engine.

Bug 1498688

Change-Id: I5ca12f64bae8f12333d82350278c700645d5007e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/422198
2015-03-18 12:10:13 -07:00
Alex Waterman
bea4bb915a gpu: nvgpu: Implement L2 flush in fifo recovery
Implement a full L2 flush (clean and invalidate) for gm20b in
the fifo recovery path.

Bug 1512176

Change-Id: Ibf89ede9cca65a6868ebff89825869053302a007
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/416435
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:10:11 -07:00
Lauri Peltonen
f575bc6676 gpu: nvgpu: Support semaphore sync when aborting jobs
When aborting jobs on channel error situations, we manually set
the channel syncpoint's min == max in gk20a_disable_channel_no_update.
Nvhost will notice this manual syncpoint increment, and will call back
to gk20a_channel_update, which will clean up the job.

With semaphore synchronization, we don't have anybody calling back to
gk20a_channel_update, so we need to call it ourselves. Release job
semaphores (the equivalent of set_min_eq_max) on
gk20a_disable_channel_no_update, and if any semaphores were released,
call gk20a_channel_update afterwards.

Because we are actually calling gk20a_channel_update in some situations,
gk20a_disable_channel_no_update is no longer an appropriate name for the
function. Rename it to gk20a_channel_abort.

Bug 1450122

Change-Id: I1267b099a5778041cbc8e91b7184844812145b93
Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com>
Reviewed-on: http://git-master/r/422161
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:10:10 -07:00
Terje Bergstrom
cd13ee4aaf gpu: nvgpu: Set ch error before channel disable
In error case we first disabled the channel, and reset sync point to
max. After this we set channel error state. This causes a race if
channel is closed between setting sync point and setting channel
state.

Rearrange the code so that error state is set first, and only then
channel is disabled.

Bug 1519646

Change-Id: I20550f6a2708f892b6ba4ee714e90bdecdd128ad
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/418948
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
2015-03-18 12:10:05 -07:00
Terje Bergstrom
28c35a1b99 gpu: nvgpu: Fault engines on PBDMA error
On PBDMA error even though the engine might not be wedged, we need to
kick the channel out of engine. Add that logic. Also when channel is
not in engine, we need to remove it from runlist.

Bug 1498688

Change-Id: I5939feb41d0a90635ba313b265c7e3b5d3f48622
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/417682
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
2015-03-18 12:10:03 -07:00
Terje Bergstrom
5dc7fd0243 gpu: nvgpu: Handle PBDMA errors
Add handling for PBDMA errors.

Bug 1498688

Change-Id: Iff391110db1c270c05c76e6a14b7c666da8e3751
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:09:59 -07:00
Terje Bergstrom
24fc5e36a7 gpu: nvgpu: Initialize FECS explicitly on recovery
Instead of calling second phase of PMU boot sequence, initialize FECS
directly.

Change-Id: I7f9de0c5ec42049033839d244979f3f3daabf317
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/410204
2015-03-18 12:09:56 -07:00
Terje Bergstrom
145a9edd3f gpu: nvgpu: Ignore lbreq interrupt
Even though we mask LBREQ interrupt, hardware will still indicate it
in PBDMA interrupt register. Stop treating LBREQ as fatal.

Bug 1498688

Change-Id: Iec4c199437c50951ed9289cb85faf0008646d5c0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/408763
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>
2015-03-18 12:09:21 -07:00
Terje Bergstrom
9a6cc07c55 gpu: nvgpu: Do not enable lbreq interrupt
Lbreq interrupt can assert when there is memory back pressure. Do not
enable it as either stalling or nonstalling interrupt.

Bug 1498688

Change-Id: I02f94a64ab9df82402d80a632450d87457644d50
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/408040
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
2015-03-18 12:09:21 -07:00
Terje Bergstrom
3cebc5758a gpu: nvgpu: Fix sched error and recovery race
Fix race between channel recovery and sched error.

Bug 1499214

Change-Id: If95526c7e374703e8941f1b24d3916384261058e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/405662
(cherry picked from commit f8092e158294260dd9d041dc7f4d2c1872e02474)
Reviewed-on: http://git-master/r/407571
Reviewed-by: Automatic_Commit_Validation_User
2015-03-18 12:09:20 -07:00
Terje Bergstrom
3df84a13d1 gpu: nvgpu: Make trigger mmu fault GPU specific
Add abstraction for triggering fake MMU fault, and a gk20a
implementation. Also adds recovery to FE hardware warning
exception to make testing easier.

Bug 1495967

Change-Id: I6703cff37900a4c4592023423f9c0b31a8928db2
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:09:06 -07:00
Arto Merilainen
a9785995d5 gpu: nvgpu: Add NVIDIA GPU Driver
This patch moves the NVIDIA GPU driver to a new location.

Bug 1482562

Change-Id: I24293810b9d0f1504fd9be00135e21dad656ccb6
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/383722
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:08:53 -07:00