Move ptimer unit HALS outside gk20a.h. This is required for
documenting the HALs. We divide the ptimer unit HALs into 3 categories:
1. Private HALs
2. FUSA HALs
3. NON-FUSA HALs
This classification will help focus only on FUSA HALs in design
document and exclude the non-safety related ones from design
document.
Add ptimer HAL header file which contains the HALs exposed by ptimer
unit.
Use @cond...@endcond to skip documentation for NON-FUSA HALs and
private HALs from ptimer unit.
Add doxygen comments for
1. ptimer unit's public HAL used in safety build
a. ptimer.isr
2. ptimer unit's public APIs
a. ptimer_scalingfactor10x()
b. ptimer_scale()
JIRA NVGPU-2503
Change-Id: If5fb00733e122b27826ec36503f175fae172c71b
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2219427
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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In the change_seq of latest ucode, the boot pstate
index was taken from pstate board_objs instead of the
value from change_input. This forces the need of
introducing boot index in pstate board_obj structure.
The index is the performance table entry index of
P0 pstate.
The ucode change is described in P4CL #27304645
NVGPU-4081
Change-Id: Id3f4a1da7015cd6b7efe555529f1fa13c9f3b391
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2202363
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Currently nvgpu reads the temperature by reading the
NV_THERM_I2CS_SENSOR_00 register. Below are the issues
with current approach
1) NV_THERM_I2CS_SENSOR_00 doesn't support
fractional precision which is POR.
2) It doesn't support negative temperatures which
is required for Auto.
3) It doesn't take into account the right POR
sensor in VFE VBIOS tables.
From therm channel get status interface we can read the
current temperature from PMU.
NVBUG - 200549047
Change-Id: I2fb21926208876f3d3bebe3f2dee08edafedbc7d
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2196224
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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This patch brings a number of changes to the mm.vm unit test:
- test_map_buf: add steps to check for error cases and increase
coverage.
- test_map_buf_gpu_va: add steps to check for error cases and
increase coverage.
- test_init_error_paths: new test to target all possible error
paths in the VM init code.
- test_map_buffer_error_cases: new test to target all possible
error paths in the buffer mapping logic.
- test_nvgpu_vm_alloc_va: new test to target the nvgpu_vm_alloc_va
API and also target error paths.
- test_vm_bind: new test to target the nvgpu_vm_bind_channel API
and also target error paths.
- test_vm_aspace_id: new test to target the vm_aspace_id API
and also target error paths.
JIRA NVGPU-909
Change-Id: I755c89a6de09376d2624130a98966c172d850bfe
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2217679
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There are 2 instances where some code is unreachable in vm.c
- The nvgpu_insert_mapped_buf function always returned 0, so any
associated error handling was unreachable. This patch changes
the function to return void instead.
- A cleanup section to unmap a buffer in case of error was also
unreachable.
JIRA NVGPU-909
Change-Id: I6d8343b2994d314992a61dd640b10e68fbbc5e1e
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2217677
Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
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Update struct nvgpu_fecs_ecc_status comments for doxygen.
Move structures for method, mailbox and cond outside
the nvgpu_fecs_method_op struct, for better doxygen
format. Defining sturct within struct doesnot look
good in doxygen.
Jira NVGPU-4107
Change-Id: I34b2249119e5578c568139f958e6edab9d75d7c8
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2219748
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This move is required for documenting the HALs. We divide the
Top unit HALs into 3 categories:
1. Private HALs
2. FUSA HALs
3. NON-FUSA HALs
This classification will help focus only on FUSA HALs in design
document and exclude the non-safety related ones from design
document.
Also, add this HAL header file to yaml.
JIRA NVGPU-2500
Change-Id: I8325b4bb2677cba9be94e15ec2683d1c9e0bc68e
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2215228
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Add more doxygen to common members of struct gk20a. Use @cond/@endcond
to limit inclusion of non-FUSA members. There's a number of
unit-specific members that are still undocumented.
JIRA NVGPU-2532
Change-Id: Ie0cb419e620b08405f9ed5890c712a937eb5c88d
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2220456
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Update defaults header to include doxygen documentation
for various default values used in NvGPU.
Currently, the header defines default values only for
timeouts.
JIRA NVGPU-2418
Change-Id: I4a29024dc6bf19c32a5070d0d75aa84ddebc3379
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2219271
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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-Renamed ACR structs for FUSA, ACR FUSA code has struct names
ending with _v1 & ACR non-FUSA with _v0, removed _v1 for FUSA
code to keep struct without any versioning for doxygen.
-Renamed acr_blob_construct_v1.c/h to acr_blob_construct.c/h
JIRA NVGPU-2516
Change-Id: Id2d5e48e8169ce59371c2b08d04c5a65ba94c685
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2218265
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Add NVGPU_INIT_TABLE_ENTRY for nvgpu_sw_quiesce_init_support.
Add g->sw_quiesce_init_done to avoid multiple initializations,
and check if deinit is needed in nvgpu_sw_quiesce_remove_support.
This avoids issues in common.init unit tests.
Jira NVGPU-4089
Change-Id: Ife3aa43d5f1f86899a895e4576e38ecc28a8e371
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2217779
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For MMU and PBDMA faults, error notifier needs to be set
before entering SW quiesce. Otherwise it ends up with
default NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT.
Added nvgpu_rc_mmu_fault to:
- call g->ops.fifo.recover when recovery is enabled
- set MMU error when recovery is disabled
Updated nvgpu_rc_pbdma_fault to set PBDMA error when
recovery is disabled as well.
Wait for deferred interrupts to complete before actually
entering SW quiesce state, to make sure error notifier has
been set.
Jira NVGPU-4127
Change-Id: Ia84c723e021e397391c6c609d4bb96c06afdcc47
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2210909
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Disable CONFIG_NVGPU_RECOVERY for safety build.
Uncorrectable errors will cause the GPU to be put gracefully into
a non-functioning state to ensure that no corrupted work is
completed because of the fault. This is because the freedom
from interference may not always be shown between the faulted and
the non-faulted TSG contexts.
Jira NVGPU-4089
Change-Id: Ice60722a3be3df980ac81c26f1370f22192bab36
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2197255
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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