Vedashree Vidwans
cd7194cbc0
gpu: nvgpu: modify gmmu page table entry functions
...
Move below chip agnostic gmmu pte functions to common/mm/gmmu/pte.c.
- gmmu_aperture_mask()
- pte_dbg_print()
Default big page size for all chips is 64K. So, move
gp10b_mm_get_default_big_page_size() to common file and rename as
nvgpu_gmmu_default_big_page_size().
Modify gv11b_gpu_phys_addr() to use get_iommu_bit() hal.
JIRA NVGPU-4666
Change-Id: I512c42723faf2d03e5b367879c9c385dcf52cdc2
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2329560
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2020-12-15 14:13:28 -06:00
Philip Elcan
cf8707e2b3
gpu: nvgpu: mm: add hal to get max page table levels
...
Add a HAL API to get the maximum page table levels for the current
hardware.
JIRA NVGPU-3489
Change-Id: I1635ca576f3db461afb8e4e46db1e8912bcfdcd6
Signed-off-by: Philip Elcan <pelcan@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2224449
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2020-12-15 14:10:29 -06:00
Philip Elcan
66c79f3bb3
gpu: nvgpu: mm: use u64 for get_mmu_levels()
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Change the big_page_size parameter for the HAL API get_mmu_levels from
u32 to u64. This eliminates a CERT-C INT31 violation in page_table.c for
casting without checking the value.
JIRA NVGPU-3515
Change-Id: If001407666acd21733017f420e615ae6bd6d929c
Signed-off-by: Philip Elcan <pelcan@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2125026
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2019-05-29 12:59:40 -07:00
Alex Waterman
00d7b53b73
gpu: nvgpu: Move remaining GMMU HAL code to hal/mm/gmmu/
...
Move the remaining GMMU HAL related code from the gm20b/, gp10b/,
and gv11b/ directories to new gmmu hal source files.
Also update all makefiles and HAL init code to refelct the new
location of the headers and source code.
JIRA NVGPU-2042
Change-Id: Ic9b85cc547bd0f994ad11042fc4093c517327399
Signed-off-by: Alex Waterman <alexw@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2103672
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2019-04-26 09:36:26 -07:00
