2 Commits

Author	SHA1	Message	Date
Sagar Kamble	9bb347edec	gpu: nvgpu: fix the hw header accessors ... Various gv11b register accessors are passed as function pointer to NVGPU_ECC_ERR. pmu logic needs access to head, tail, mutex registers as function pointers. fix the same. JIRA NVGPU-3733 Change-Id: I5668fedaac187fab052ee5d68a10f7e2d6d35413 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2150880 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-07-12 06:20:44 -07:00
Mahantesh Kumbar	2cf8feedd8	gpu: nvgpu: Create PMU HAL ... Moved PMU HAL code from common/pmu/pmu_chip.c/h to hal at path hal/pmu/pmu_chip.c/h file. some code may need more cleanup but will take care in new patches JIRA NVGPU-2002 Change-Id: I281a2c15e55292e0716b0a4c71f4469c97dd71ab Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2089410 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-04-16 02:54:46 -07:00