Deepak Nibade
fae1f20ab7
gpu: nvgpu: update tu104 regops allowlist
...
Sync tu104 regops allowlist to latest allowed values.
Bug 200605637
Change-Id: I6287cf4deb74418d5d25aef5a19259cc4813c80c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2476116
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com >
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Reviewed-by: Alex Waterman <alexw@nvidia.com >
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GVS: Gerrit_Virtual_Submit
2021-01-29 08:00:46 -08:00
Mayur Poojary
160c6c16bd
gpu: nvgpu: Add auto-generated regops allowlist
...
Add auto-generated regops allowlist files for gv11b and tu104.
Update Makefiles accordingly.
Bug 2510974
Bug 200668999
Jira NVGPU-5360
Change-Id: I5bc6a220ef6f90838e0ba735b1ee8e97d8f9215f
Signed-off-by: Mayur Poojary <mpoojary@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2423637
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
Reviewed-by: Deepak Nibade <dnibade@nvidia.com >
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2020-12-15 14:13:48 -06:00
Deepak Nibade
1ff79b1d2c
gpu: nvgpu: remove support for quad reg_op
...
quad type reg_ops were only needed on Kepler, and not for any other chip
beginning Maxweel.
HAL g->ops.gr.access_smpc_reg() was incorrectly set for Volta and Turing
whereas it was only applicable to Kepler. Delete it.
There is no register in the quad type whitelist since the type itself is
not supported anymore. Remove the empty whitelists for all chips and
also delete below HALs:
g->ops.regops.get_qctl_whitelist()
g->ops.regops.get_qctl_whitelist_count()
hal/regops/regops_gv100.* files are not used anymore. Delete the files
instead of just deleting quad HALs in these files.
Bug 200628391
Change-Id: I4dcc04bef5c24eb4d63d913f492a8c00543163a2
Signed-off-by: Deepak Nibade <dnibade@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2366035
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2020-12-15 14:13:28 -06:00
Deepak Nibade
67350e2c9c
gpu: nvgpu: add flags to debugger specific headers
...
Add debugger/cyclestats/fecs_trace compile time flags to debugger
specific unit headers
Jira NVGPU-3506
Change-Id: Iedea5f274243a389dce91edecbc80c58753d4805
Signed-off-by: Deepak Nibade <dnibade@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2137253
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2019-06-18 01:38:54 -07:00
Deepak Nibade
840972c1cc
gpu: nvgpu: update TU104 regops whitelist
...
List of whitelisted registers is auto generated with script
Bug 200526741
Change-Id: I097f4638ce9c1498ae09cfea2dbc7386fc5e0004
Signed-off-by: Deepak Nibade <dnibade@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2135669
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com >
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com >
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com >
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2019-06-13 09:35:55 -07:00
Deepak Nibade
88c8baa29f
gpu: nvgpu: create common.hal.regops unit
...
Create common.hal.regops unit by moving all regops chip files under
hal/ directory
Update Makefiles and include paths accordingly
Jira NVGPU-2037
Change-Id: Iac1833b8916d919f7d448d17f5dd7a853760f55c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2094288
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2019-04-12 04:05:04 -07:00
