Add support for interrupt unit tests for following use cases
1. with channel and without tsg.
2. with channel and tsg, without setting the context to local cache.
3. with channel and tsg, setting the context to local cache
Jira NVGPU-4096
Change-Id: Ib9e5b49f5c5b94d785b9e225a84f3b2829fd3cf7
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2213089
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Rename gr register space allocation and deallocation functions
to test_gr_init_setup and test_gr_remove_setup
Add tests to support following functions
nvgpu_gr_init
nvgpu_gr_init_support
nvgpu_gr_suspend
nvgpu_gr_remove_support
Jira NVGPU-3970
Change-Id: I11418ddcb9946ef75de162fd5689fdbbbfb62e79
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2194612
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When the non-FUSA HALs were removed, the entire fuse unit test was
removed. However, some of the fuse HALs are used in the FUSA build, so
re-enable the FUSA tests, as appropriate.
JIRA NVGPU-3943
Change-Id: I6656940492102ace335672466592b22ed9ce95fd
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2194569
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Move gr_init_prepare to separate gr unit test
Use of global register spaces between two different
gr unit tests corrupt the memory in multi thread support.
Add support for local register spaces with pre initialized
register values for each gr unit test.
Jira NVGPU-3582
Change-Id: I4e47c1ca4f312335cd33a73a377f9fa9f12ccd5f
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2189502
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This reverts commit 9bfdb2ba03f90f0cf828f08b99101a3a3e6c4532.
Bug 2693908
Change-Id: I3ef56773e46aad3626f16b84ea5e51c2fdcc3f1c
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2189200
Add support gr_prepare for sw and hw.
Add needed registers using nvgpu_posix_io_add_reg_space calls.
Add unit tests covering following functions
nvgpu_gr_prepare_sw
nvgpu_gr_enable_hw
Copy the falcon ucode binaries under userspace/firmware
directory
install-unit.sh modified to copy the firmware binaries
under nvgpu-unnit/firmware directory
Jira NVGPU-3582
Change-Id: If2131d2c48e828251208da86688b0594e62de82e
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2184293
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Safety build does not support vidmem. This patch compiles out vidmem
related changes - vidmem, dma alloc, cbc/acr/pmu alloc based on
vidmem and corresponding tests like pramin, page allocator &
gmmu_map_unmap_vidmem..
As vidmem is applicable only in case of DGPUs the code is compiled
out using CONFIG_NVGPU_DGPU.
JIRA NVGPU-3524
Change-Id: Ic623801112484ffc071195e828ab9f290f945d4d
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132773
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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Since DGPU support is not available in safety build now let us skip
the gv100 fuse unit tests on that build using CONFIG_DGPU_SUPPORT.
Remove these tests from required_tests.json as well.
JIRA NVGPU-3062
Change-Id: I7ec7cd1164af8c44d798f8906aa0be89f480dca2
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120275
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Add a threaded test for nvgpu_cmpxchg API. This test implements an
atomic increment using cmpxchg. It uses the existing arithmetic
threaded framework to use the cmpxchg_inc() function to verify 100
parallel threads increment the atomic the correct number of times.
These are L1 tests since they have longer run times and are unlikely to
regress.
JIRA NVGPU-2251
Change-Id: I9c2b68052b3a1b6ef20adfa24e7d50746902f754
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100748
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Add a threaded test to verify xchg operation. Also validate the
non-atomic version will fail.
There are 100 threads spawned that each do exchanges on the same atomic
1000 times. Each thread starts with a unique value. When the test
completes, make sure the values are still unique.
These are L1 tests since they have longer run times and are unlikely to
regress.
JIRA NVGPU-2251
Change-Id: I4741df500d712e60d92e5221182be02dbeaa14ef
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2081067
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Add threaded tests for inc_and_test, dec_and_test, and sub_and_test
operations to verify atomicity. Also, add non-atomic tests for these to
verify we are actually verifying that the operations are atomic.
The new tests initialize an atomic to a non-zero value such that the
threads executing the atomic operation will reach and pass zero. The
test verifies only 1 thread observed zero (the atomic operation
returned true). The test is executed 5000 times with 100 threads.
For example, the inc_and_test will start the atomic at -50 and 100
threads will concurrently increment the atomic. The test will verify
only one of the 100 threads observed 0.
These tests are L1 tests since we don't expect regressions in the
atomics (they are basically reusing the GCC builtins) and have longer
run times in order to make sure the non-atomic variants fail.
JIRA NVGPU-2251
Change-Id: I7811779bc7c0965b4465d420066f3cff87bfa13e
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2079378
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Unit test to target the interface.bsearch unit. The goal here is to
provide line coverage for the unit. Considering that the underlying
implementation is using POSIX's bsearch, there is no need to verify
the behavior of bsearch in depth.
JIRA NVGPU-2265
Change-Id: I93ec3193bb0f93aaa47aa0c6c44eca09320893ca
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2078427
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While resolving MISRA 10.8 violations in our definitions of U8_MAX,
U16_MAX, etc, some of the variants tried that looked valid created
invalid values due to integer promotions. So, for sanity, we should
validate these macros in the unit test for posix-env.
JIRA NVGPU-2955
Change-Id: I9c4b66771a875728c2bf79036e9a510bbc871bfb
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2078365
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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Reviewed-by: Adeel Raza <araza@nvidia.com>
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