gr config is allocated and initialized as part of gr_init_setup_sw().
The sw setup is done before gr_init_setup_hw() where sm id table
is initialized. This makes the gr_config == NULL check redundant.
Fix the coverity issue (dereference before null check) by removing
the redundant check.
JIRA NVGPU-4026
Change-Id: I16a8700ff5fee524c2e32e75b621e74c59c8e44f
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2199360
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Add macros for whitelisting coverity violations. These macros use pragma
directives. The pragma directives and whitelisting macros are only
enabled when a coverity scan is being run.
The whitelisting macros have been added to a new header called
static_analysis.h. The contents of safe_ops.h (CERT C safe ops) have
been moved into static_analysis.h because this will be the new header
for static analysis related macros/defines/etc.
JIRA NVGPU-3820
Change-Id: I9c63f20f670880b420415535738034619314b7c3
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2180600
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Fix MISRA 8.6 violation in gr config and interrupt units.
Rule 8.6 requires each identifier with external linkage to have
exactly one external definitions.
Move unused function definitions under CONFIG_NVGPU_HAL_NON_FUSA
checking.
Jira NVGPU-3854
Change-Id: I0661ea00ef9df700b0b928c8bf77e9a0fa4be29b
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2171386
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reduce code complexity of following functions in gr.config unit
gv100_gr_config_init_sm_id_table(complexity : 13)
gr_gv100_scg_estimate_perf(complexity : 23)
Create sub functions by moving the control statement codes
from the function which has high complexity above 10.
Create two sub functions from gv100_gr_config_init_sm_id_table function
gr_gv100_scg_estimate_perf_for_all_gpc_tpc(complexity : 5)
gv100_gr_config_set_sminfo(complexity : 3)
and reduce gv100_gr_config_init_sm_id_table complexity to 8
Create four sub functions from
gv100_gr_config_init_sm_id_table function
gr_gv100_find_max_gpc(with complexity : 2)
gr_gv100_remove_logical_tpc(with complexity : 4)
gr_gv100_calc_valid_pes(with complexity : 6)
gr_gv100_scg_calculate_perf(with complexity : 7)
and reduce gr_gv100_scg_estimate_perf complexity to 10
Jira NVGPU-3661
Change-Id: Iaaef1a98f2c6c55cd7b0a1a57d1c74eb09d43869
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2156744
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This patch moves all the safe static and non-static functions as well
as its dependencies such as static declared structs into files with
_fusa.c extension. If the original file is left with no functions
remaining then the file is deleted.
Added changes in Makefile, Makefile.sources, nvgpu-hal-new.yaml for
compilation.
Jira NVGPU-3690
Change-Id: I81af67c308705faf8a681df63a6778e7de2076cf
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2146761
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Below MISRA 10.3 violation is reported in hal.gr.config unit
Error: MISRA C-2012 Rule 10.3:
nvgpu/drivers/gpu/nvgpu/hal/gr/config/gr_config_gv100.c:174:
misra_violation: Implicit conversion of "pix_scale * min_scg_gpc_pix_perf + world_scale *
scg_world_perf + tpc_scale * tpc_balance" from essential type "unsigned 32-bit int" to different
or narrower essential type "signed 32-bit int".
Fix this by declaring corresponding variables u32.
This should have no functional impact as such
Jira NVGPU-3406
Change-Id: I5b66c8db25c33afec3ab622a8d45997d5c8e6daa
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115591
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Below MISRA 10.3 violation is reported in hal.gr.config unit
Error: MISRA C-2012 Rule 10.3:
nvgpu/drivers/gpu/nvgpu/hal/gr/config/gr_config_gv100.c:150:
misra_violation: Implicit conversion of "(int)average_tpcs - scale_factor * num_tpc_gpc[gpc_id]"
from essential type "unsigned 32-bit int" to different or narrower essential type "signed 32-bit int".
Fix this by converting "diff" variable to u32 and checking for greater
value before doing subtraction operation
Jira NVGPU-3406
Change-Id: I27695db5bd3a4f20db878888dc87dc78ff04888a
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115590
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Below MISRA 10.3 violations are reported in hal.gr.config unit
Error: MISRA C-2012 Rule 10.3:
nvgpu/drivers/gpu/nvgpu/hal/gr/config/gr_config_gv100.c:72:
misra_violation: Implicit conversion of "gpc_tpc_mask[gpc_id]" from essential type
"unsigned 64-bit int" to different or narrower essential type "unsigned 32-bit int".
gpc_tpc_mask[] and tpc variables should really be u32, hence declare
them as u32 everywhere
for_each_set_bit() takes parameters as unsigned long
Use temporary unsigned long variables in above macro and then
explicitly cast them to/from u32
Jira NVGPU-3406
Change-Id: Idd1dc2ba95bd1f6a3968a0103f0ec4914101f629
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115589
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
MISRA Rule 14.2 requires for loop to be well-formed. A well-formed for
loop has below requirements:
1. first clause can be empty or should assign value to a single loop
counter
2. second clause should exist and use loop counter or loop control flag.
It should not use any variable modified in the loop body.
3. third cluase should only update loop counter and should not use
objects modified in the loop body.
This modifies for loops to process single loop counter. The patch moves
additional initializations before for loop, conditions at loop start
and variable updates at the end of for loop.
Jira NVGPU-855
Change-Id: I93ccf1ac0677ff355364a718d2d953467f1d9d95
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2108188
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Below 5.7 violations are reported in common.gr.config unit :
nvgpu/drivers/gpu/nvgpu/common/gr/gr_config.c:628:
identifier_reuse: Identifier "sm_info" is already used to represent a type.
Fix them by renaming struct sm_info to struct nvgpu_sm_info
Jira NVGPU-3225
Change-Id: I26f70a4ed2a5a845e0dc9daeb8fb5474e35d42fb
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110986
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Remove use of struct gk20a and struct gr_gk20a from common.gr.config
hal functions.
This requires a reference to struct gk20a *g for many nvgpu_* ops. Also,
nvgpu_gr_config is updated to include sm_count_per_tpc.
JIRA NVGPU-1884
Change-Id: I874c2b3970d97ef3940b74d8ef121a7261061670
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2075681
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
