Commit Graph

13 Commits

Author SHA1 Message Date
Divya
ef1fb41e54 gpu: nvgpu: add pmu hals to resolve mismatch
Add the following HALs to avoid the duplication
of code for future chips:
- set_mailbox1
- get_ecc_address
- get_ecc_status
- set_ecc_status

JIRA NVGPU-9758

Change-Id: I54ce3dfaae2873dbcd88edabbd877eca9f3d1fdb
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2898016
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2023-05-16 06:27:08 -07:00
vivekku
a687c78077 gpu: nvgpu: exit PMU functions if PMU state is OFF
Add a condition to exit PMU functions if PMU FW state is
Set to OFF as these functions could be called from main
GPU thread or pg task thread but PMU sub-unit is exited
as part of power off sequence.

Bug 3812500

Change-Id: I8e8de411e1cb2b0ffe1991814ce8209113490272
Signed-off-by: vivekku <vivekku@nvidia.com>
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2789329
(cherry picked from commit 71253495bf994c1e17ea18146451b50e4e64bba5)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2789518
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Tested-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
2022-11-22 21:56:51 -08:00
mkumbar
ff3823eeb4 gpu: nvgpu: ga10b: LSPMU interrupt update
Enable/disable LSPMU interrupt in MC, as required LSPMU
interrupts are configured as part of LSPMU ucode init and
don't need any additional PMU IRQ register to set/clear as
part of GPU power-on/off sequence.

Bug 3681561

Change-Id: Ifb47bc9cc83e16e46649b0eef5f257acb02f302c
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2739476
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
2022-07-06 19:01:22 -07:00
Richard Zhao
1ce899ce46 gpu: nvgpu: fix compile error of new compile flags
Preparing to push hvrtos gpu server changes which requires bellow CFLAGS:
        -Werror -Wall -Wextra \
        -Wmissing-braces -Wpointer-arith -Wundef \
        -Wconversion -Wsign-conversion \
        -Wformat-security \
        -Wmissing-declarations -Wredundant-decls -Wimplicit-fallthrough

Jira GVSCI-11640

Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: I25167f17f231ed741f19af87ca0aa72991563a0f
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2653746
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
2022-05-07 15:11:49 -07:00
mkumbar
0b9dc3dbc3 gpu: nvgpu: PMU NVRISCV engine HSI support
Below listed HSI are handled with PMU ISR handler and
all these triggers interrupt from individual unit upon issue.

-Add ECC check for IMEM, DMEM, DCLS, REG, and MPU as per
 HSI req
-Add MEMERR check for GPU_PMU_ACCESS_TIMEOUT_UNCORRECTED
 PMU HSI id
-Add IOPMP check for GPU_PMU_ILLEGAL_ACCESS_UNCORRECTED
 PMU HSI id
-Add WDT check for GPU_PMU_WDT_UNCORRECTED PMU HSI id

Bug 3491596
Bug 3366818

Change-Id: I751d653e447017ac62a2459da2c6bb9da506f438
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2686566
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2022-03-25 13:25:39 -07:00
mpoojary
4e98b53944 gpu: nvgpu: ga10b: Update ga10b_is_pmu_supported
Update ga10b_is_pmu_supported function to add support
for pre-si platforms along with silicon.

JIRA NVGPU-4701

Change-Id: If7eec7753c01135c9c9c20d49278b3f1fe9332ae
Signed-off-by: mpoojary <mpoojary@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2652871
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2022-01-13 19:30:46 -08:00
Richard Zhao
e81a36e56a gpu: nvgpu: hal: fix compile error of new compile flags
It's preparing to add bellow CFLAGS:
    -Werror -Wall -Wextra \
    -Wmissing-braces -Wpointer-arith -Wundef \
    -Wconversion -Wsign-conversion \
    -Wformat-security \
    -Wmissing-declarations -Wredundant-decls -Wimplicit-fallthrough

Jira GVSCI-11640

Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: Ia16ef186da1e97badff9dd0bf8cbd6700dd77b15
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2555057
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-by: Aparna Das <aparnad@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2022-01-13 12:36:19 -08:00
mkumbar
61c6aeec41 gpu: nvgpu: disable LSPMU for ga10b safety
Bug 3456240

Change-Id: I0bb9581d2df46e5cb2dea57794ee0c918394eb66
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2645646
(cherry picked from commit aab86a06485c94546e11809cdeeefe9906e9b680)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2629878
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Shashank Singh <shashsingh@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2022-01-06 17:19:46 -08:00
Mahantesh Kumbar
ce7d589a4d gpu: nvgpu: ga10b: add PMU interrupt check hal
-GA10B PMU IRQ registers are not accessible when NVRISCV PRIV lockdown
 is engaged, so need to skip accessing IRQ registers.

NVGPU-7061

Change-Id: If5233e502a9bef838839376c412582e08d729a99
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2636964
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-12-06 04:37:39 -08:00
Deepak Nibade
3d9c67a0e7 gpu: nvgpu: enable Orin support in safety build
Most of the Orin chip specific code is compiled out of safety build
with CONFIG_NVGPU_NON_FUSA and CONFIG_NVGPU_HAL_NON_FUSA. Remove the
config protection from Orin/GA10B specific code. Currently all code
is enabled. Code not required in safety will be compiled out later
in separate activity.

Other noteworthy changes in this patch related to safety build:

- In ga10b_ce_request_idle(), add a log print to dump num_pce so that
  compiler does not complain about unused variable num_pce.
- In ga10b_fifo_ctxsw_timeout_isr(), protect variables active_eng_id and
  recover under CONFIG_NVGPU_KERNEL_MODE_SUBMIT to fix compilation
  errors of unused variables.
- Compile out HAL gops.pbdma.force_ce_split() from safety since this HAL
  is GA100 specific and not required for GA10B.
- Compile out gr_ga100_process_context_buffer_priv_segment() with
  CONFIG_NVGPU_DEBUGGER.
- Compile out VAB support with CONFIG_NVGPU_HAL_NON_FUSA.
- In ga10b_gr_intr_handle_sw_method(), protect left_shift_by_2 variable
  with appropriate configs to fix unused variable compilation error.
- In ga10b_intr_isr_stall_host2soc_3(), compile ELPG function calls
  with CONFIG_NVGPU_POWER_PG.
- In ga10b_pmu_handle_swgen1_irq(), move whole function body under
  CONFIG_NVGPU_FALCON_DEBUG to fix unused variable compilation errors.
- Add below TU104 specific files in safety build since some of the code
  in those files is required for GA10B. Unnecessary code will be
  compiled out later on.
	hal/gr/init/gr_init_tu104.c
	hal/class/class_tu104.c
	hal/mc/mc_tu104.c
	hal/fifo/usermode_tu104.c
	hal/gr/falcon/gr_falcon_tu104.c
- Compile out GA10B specific debugger/profiler related files from
  safety build.
- Disable CONFIG_NVGPU_FALCON_DEBUG from safety debug build temporarily
  to work around compilation errors seen with keeping this config
  enabled. Config will be re-enabled in safety debug build later.

Jira NVGPU-7276

Change-Id: I35f2489830ac083d52504ca411c3f1d96e72fc48
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2627048
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-11-26 08:46:47 -08:00
Mahantesh Kumbar
3880443b53 gpu: nvgpu: t234: Fix PMU IRQ reg PRIV error
-GA10B PMU IRQ registers are not accessible when NVRISCV PRIV lockdown
 is engaged, so need to skip modifying/configuring IRQ registers.
-Add new GA10B PMU HAL for PMU IRQ support.
-GA10B PMU IRQ HAL checks for PRIV lockdown and if enabled then just
 enable PMU interrupt from MC, if not enabled then follows legacy chip
 method to configure the PMU interrupt.

Bug 200780546

Change-Id: Idecf460a58b0e334f9ca2301ce8ee33b760b73c0
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2603245
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-10-01 00:51:54 -07:00
mkumbar
87984ea344 gpu: nvgpu: support nvriscv debug feature
Enable nvriscv debug buffer feature in NVGPU.
Debug buffer is a feature to print the debug log from ucode onto console
in real time.
Debug buffer feature uses the DMEM, queue and SWGEN1 interrupt to share
ucode debug data with NVGPU.
Ucode writes debug message to DMEM and updates offset in queue to trigger
interrupt to NVGPU.
NVGPU copies the debug message from DMEM to local buffer to process and
print onto console.

Debug buffer feature is added under falcon unit and required engine
can utilize the feature by providing required param through public
functions.

Currently GA10B NVRISCV NS/LS PMU ucode has support for this feature
and enabled support on NVGPU side by adding required changes, with this
feature enabled, it is now possible to see prints in real time.

JIRA NVGPU-6959

Change-Id: I9d46020470285b490b6bc876204f62698055b1ec
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2548951
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-07-17 12:45:00 -07:00
Sagar Kadamati
3e43f92f21 gpu: nvgpu: add ga10b & ga100 sources
Mass copy ga10b & ga100 sources from nvgpu-next repo.
TOP COMMIT-ID: 98f530e6924c844a1bf46816933a7fe015f3cce1

Jira NVGPU-4771

Change-Id: Ibf7102e9208133f8ef3bd3a98381138d5396d831
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2524817
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2021-06-17 12:56:16 -07:00