Currently, GVS is failing intermittently for some tests in nvgpu-runlist
and hal/mm/mmu_fault.
This patch resets gk20a structure at the end of each mmu_fault test. The
test_runlist_reload_ids and test_runlist_update_locked tests are
modified to use fifo support environment initialized for nvgpu-runlist
unit test.
Bug 2791755
Change-Id: I0b69b4f216f8f820b0a480ed76170b523b434bef
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2265676
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Following changes are done to common.top code and UT:
1.Change return type for device_info_parse_enum to void as it can never
return non-zero value.
- This is a private HAL and is only called by get_device_info HAL.
- It gets called only for table entry with entry type = enum.
- So there is no error path left.
This helps remove unnecessary branches and get better branch coverage
2. Check if the data parsing function pointers are not NULL before
parsing the device tree. Return error if there are no functions
to interpret the device_info table registers. Add checks for same in
unit test test_get_device_info().
JIRA NVGPU-2204
Change-Id: I8833da7aa58b070d19b50ee17f64362f301bd792
Signed-off-by: tkudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2269603
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MISRA rule 11.2 doesn't allow conversions of a pointer from or to an
incomplete type. These type of conversions may result in a pointer
aligned incorrectly and may further result in undefined behavior.
This patch addresses rule 11.2 violations related to pointers to and
from struct nvgpu_sgl. This patch replaces struct nvgpu_sgl pointers by
void pointers.
Jira NVGPU-3736
Change-Id: I8fd5766eacace596f2761b308bce79f22f2cb207
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2267876
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Device info data format has changed from gp10b to
gv11b, and MMU fault id was incorrectly decoded for GR engine.
Add gv11b_device_info_parse_data HAL to decode device info
data with correct field definitions.
Move gp10b device_info parse data to non-fusa, since
it is not used anymore in safety build.
Jira NVGPU-4511
Change-Id: I2b3f3b5fec977d63a9ad6cfd99c04f375cf997e8
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2262217
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Add new unit test to cover gops.gr.init.ecc_scrub_reg HAL function
gops.gr.init.ecc_scrub_reg HAL can generate TIMEOUT errors which are
not returned to caller currently. Update this HAL to return int value
for error propagation.
Jira NVGPU-4458
Change-Id: I98f4d5af2ef17cc4301951fec4d660638c8ef72c
Signed-off-by: dnibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2265456
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Use the updated test types.
Other (setup) --> Other (cleanup)
Feature based --> Feature
Also, change test names to unique identifier to avoid below errors in
SWVS:
Warning doxygenfunction: Unable to resolve multiple matches for
function 'test_xxx' with arguments () in doxygen xml output for
project 'nvgpu_doxygen'...
JIRA NVGPU-4679
Change-Id: If8a6b9ec8b26c3f99bc657bce24751b0e75fabbf
Signed-off-by: tkudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2269046
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Use the updated test types.
Other (setup) --> Other (cleanup)
Feature based --> Feature
Also, change test names to unique identifier to avoid below errors in
SWVS:
Warning doxygenfunction: Unable to resolve multiple matches for
function 'test_xxx' with arguments () in doxygen xml output for
project 'nvgpu_doxygen'...
JIRA NVGPU-4679
Change-Id: I66cda323387163a41808be09a69f625d53b744ed
Signed-off-by: tkudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2269041
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Use the updated test types.
Other (setup) --> Other (cleanup)
Feature based --> Feature
Also, change test names to unique identifier to avoid below errors in
SWVS:
Warning doxygenfunction: Unable to resolve multiple matches for
function 'test_xxx' with arguments () in doxygen xml output for
project 'nvgpu_doxygen'...
JIRA NVGPU-4679
Change-Id: Ic2701bec2eafa0e64891d5c6d404847f14c41e55
Signed-off-by: tkudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2268937
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Use the updated test types.
Other (setup) --> Other (cleanup)
Feature based --> Feature
Also, change test names to unique identifier to avoid below errors in
SWVS:
Warning doxygenfunction: Unable to resolve multiple matches for
function 'test_xxx' with arguments () in doxygen xml output for
project 'nvgpu_doxygen'...
JIRA NVGPU-4679
Change-Id: I2bddf608f22d8c9f9dd5fbde9ca39f4417839077
Signed-off-by: tkudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2267587
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Recent patches added new dependency of mock-iospace for FIFO unit tests.
However, mock-iospace binaries are generated after compiling FIFO UTs.
This leads to "cannot find -lmock-iospace" errors. This patch moves
mock-iospace compilation before FIFO UTs.
Jira NVGPU-4675
Change-Id: Ice2dc42412e06cc9e41b31bc852c220b09974ae2
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2265396
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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fbpa related functions are not supported on igpu safety. Don't
compile them if CONFIG_NVGPU_DGPU is not set.
Also compile out fb and ramin hals that are dgpu specific.
Update the tests for the same.
JIRA NVGPU-4529
Change-Id: I1cd976c3bd17707c0d174a62cf753590512c3a37
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2265402
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At present each nvgpu test unit defines its own mocked IO space. This is used to
intialize the qnx/posix IO framework. This results in unwanted redefinitions,
bloating of the binary. This patch creates a shared library which contains all
the mocked IO space definitions and it exports a function which enable units to
query, get access to the mocked IO space.
Jira: NVGPU-4520
Change-Id: Ied19f14e25274953e15a785b3a73053d84012b80
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2260042
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Add unit tests to cover the invalid falcon port access, falcon sw init
switch cases, nvgpu_falcon_set_irq, nvgpu_timeout_init failure branch
coverage.
Compile out the functions nvgpu_falcon_get_mem_size & falcon_bootstrap
as they are needed by LS PMU and VBIOS code. For iGPU safety the
falcon functions needing these will call the HAL APIs directly.
This way we avoid the unreachable code as well. Updated the
prototype of falcon bootstrap HAL API as that doesn't return
any error.
With these changes, we get 100% line coverage for common.falcon unit.
JIRA NVGPU-2214
Change-Id: I1fe653d97c1a6a1521d7da38f171928dda58c5b5
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2258311
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PMU IRQs were not enabled assuming entire functionality for LS PMU.
Debugging early init issues of PMU falcon ECC errors triggered
during nvgpu power-on will be cumbersome if interrupts are not
enabled early. FMEA analysis of the nvgpu init path also
requires this interrupt be enabled earlier.
Hence, Enable the PMU ECC IRQ early during nvgpu_finalize_poweron.
pmu_enable_irq is updated to enable interrupts differently for
safety and non-safety. PMU interrupts disabling is moved out
of nvgpu_pmu_destroy to nvgpu_prepare_poweroff. Prepared new
wrapper API nvgpu_pmu_enable_irq.
PMU ECC init and isr mutex init is moved to the beginning of
nvgpu_pmu_early_init as for safety, ls pmu code path is
disabled. Fixed the pmu_early_init dependent and mc
interrupt related unit tests.
Update the doxygen for changed functions.
JIRA NVGPU-4439
Change-Id: I1a1e792d2ad2cc7a926c8c1456d4d0d6d1f14d1a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2251732
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pwr_csb slcg, blcg gating registers are covered by pmu slcg/blcg hence
its load functions are not used. Hence, delete the generated data and
functions. slcg, blcg ctxsw_firmware and pg_gr gating reglists are
null hence delete the generated data and functions.
JIRA NVGPU-2175
Change-Id: Ib04d9845331c9a287666d3b8c974e1d3b66a7677
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2263272
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Add negative tests that inject memory allocation failures and
HAL function call errors to verify error handling path in
common.gr.obj_ctx unit.
Update common.gr.setup test to cover invalid class input while
setting preemption mode.
Jira NVGPU-4457
Change-Id: I74d1ba63ba8aace6087b51fd50e2c136822d3a00
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2260939
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