Commit Graph

5 Commits

Author SHA1 Message Date
Antony Clince Alex
c36752fe3d gpu: nvgpu: sim: make ring buffer independent of PAGE_SIZE
The simulator ring buffer DMA interface supports buffers of the following sizes:
4, 8, 12 and 16K. At present, it is configured to 4K and it  happens to match
with the kernel PAGE_SIZE, which is used to wrap back the GET/PUT pointers once
4K is reached. However, this is not always true; for instance, take 64K pages.
Hence, replace PAGE_SIZE with SIM_BFR_SIZE.

Introduce macro NVGPU_CPU_PAGE_SIZE which aliases to PAGE_SIZE and replace
latter with former.

Bug 200658101
Jira NVGPU-6018

Change-Id: I83cc62b87291734015c51f3e5a98173549e065de
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2420728
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2020-12-15 14:13:28 -06:00
Sagar Kamble
aa893ff77a gpu: nvgpu: use GPL license for linux code
Linux specific code should have GPL license.

Bug 2755169

Change-Id: I8cbf96f4be2e77fde01ef976a79ec6c578185c23
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2237105
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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2020-12-15 14:10:29 -06:00
Debarshi Dutta
17486ec1f6 gpu: nvgpu: rename tsg_gk20a and channel_gk20a structs
rename struct tsg_gk20a to struct nvgpu_tsg and rename struct
channel_gk20a to struct nvgpu_channel

Jira NVGPU-3248

Change-Id: I2a227347d249f9eea59223d82f09eae23dfc1306
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2112424
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Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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2019-05-06 02:56:53 -07:00
Deepak Nibade
0271ffd77b gpu: nvgpu: remove max_ctxsw_ring_buffer_size from nvgpu_gr
max_ctxsw_ring_buffer_size variable in struct nvgpu_gr is used to store
max ring buffer size which is then referred into linux specific code

We only use macro GK20A_CTXSW_TRACE_MAX_VM_RING_SIZE to initialize
the variable.

And max_ctxsw_ring_buffer_size does not belong to nvgpu_gr struct
anyways

Considering above remove max_ctxsw_ring_buffer_size from nvgpu_gr and
use macro directly in linux specific code

Jira NVGPU-3125

Change-Id: Ibed9901d2bde35633d9ad0df8bd08b414e075bf4
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2105653
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Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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2019-04-26 09:37:21 -07:00
Deepak Nibade
1208ad7cef gpu: nvgpu: rearrange linux specific fecs trace support
We have 3 header files for FECS tracing support
include/nvgpu/gr/fecs_trace.h : common header
include/nvgpu/ctxsw_trace.h : header that includes both common and
                              os-specific functions
os/linux/ctxsw_trace.h : linux specific header

Remove the second header since it is not needed.

Move all structures that are needed in common code to
include/nvgpu/gr/fecs_trace.h
Move all function declarations that are needed in common code to
include/nvgpu/gr/fecs_trace.h
Move all linux specific declarations in os/linux/ctxsw_trace.h and
rename this file as os/linux/fecs_trace_linux.h

Also rename os/linux/ctxsw_trace.c to os/linux/fecs_trace_linux.c

Jira NVGPU-1880

Change-Id: I05cc4489c4b6a64880b7d59c02b22cd2244d5e22
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2070766
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2019-03-16 05:05:32 -07:00