For ASIL-D decomposision we need hw register checker to validate
potential register configurations done at init phase
This is the tool used to generate hw registers table that needs to be
validated on the target.
* Generate register list
- register addresses are picked from hw headers
- register value masks are hardcoded for validation
Jira NVGPU-8885
Change-Id: I875735b6ae6b5e94eb85e67ca802a23b7d250598
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2823929
Reviewed-by: Alex Waterman <alexw@nvidia.com>
