2 Commits

Author	SHA1	Message	Date
Philip Elcan	725daf3400	gpu: nvgpu: pmu: fix MISRA 10.3 issues in pstate ... MISRA Rule 10.3 prohibits implicit assignment of an object of different essential type or narrower type. This change addresses a number of miscellaneous violations in pstate.c JIRA NVGPU-1008 Change-Id: Iccde60d0110681f72f37dc64b2e67983757ad563 Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1995882 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-01-18 13:54:45 -08:00
Terje Bergstrom	dce78f7332	gpu: nvgpu: Move PMU code to common/pmu ... Move code interfacing with PMU tasks to common/pmu. JIRA NVGPU-961 Change-Id: Ie62611b0ffe1196d4bfdc740e03017e1894a834f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1950991 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-01-10 20:09:55 -08:00