mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-22 09:12:24 +03:00
108 lines
3.1 KiB
C
108 lines
3.1 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/vgpu/vgpu.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/vgpu/vgpu_ivc.h>
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#include "intr_vgpu.h"
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#include "common/vgpu/gr/fecs_trace_vgpu.h"
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#include "common/vgpu/fifo/fifo_vgpu.h"
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#include "common/vgpu/fifo/channel_vgpu.h"
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#include "common/vgpu/fifo/tsg_vgpu.h"
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#include "common/vgpu/mm/mm_vgpu.h"
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#include "common/vgpu/gr/gr_vgpu.h"
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int vgpu_intr_thread(void *dev_id)
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{
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struct gk20a *g = dev_id;
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struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
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while (true) {
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struct tegra_vgpu_intr_msg *msg;
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u32 sender;
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void *handle;
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size_t size;
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int err;
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err = vgpu_ivc_recv(TEGRA_VGPU_QUEUE_INTR, &handle,
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(void **)&msg, &size, &sender);
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if (err == -ETIME) {
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continue;
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}
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if (err != 0) {
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nvgpu_do_assert_print(g,
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"Unexpected vgpu_ivc_recv err=%d", err);
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continue;
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}
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if (msg->event == TEGRA_VGPU_EVENT_ABORT) {
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vgpu_ivc_release(handle);
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break;
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}
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switch (msg->event) {
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case TEGRA_VGPU_EVENT_INTR:
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if (msg->unit == TEGRA_VGPU_INTR_GR) {
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vgpu_gr_isr(g, &msg->info.gr_intr);
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} else if (msg->unit == TEGRA_VGPU_INTR_FIFO) {
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vgpu_fifo_isr(g, &msg->info.fifo_intr);
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}
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break;
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#ifdef CONFIG_NVGPU_FECS_TRACE
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case TEGRA_VGPU_EVENT_FECS_TRACE:
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vgpu_fecs_trace_data_update(g);
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break;
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#endif
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case TEGRA_VGPU_EVENT_CHANNEL:
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vgpu_tsg_handle_event(g, &msg->info.channel_event);
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break;
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case TEGRA_VGPU_EVENT_SM_ESR:
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vgpu_gr_handle_sm_esr_event(g, &msg->info.sm_esr);
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break;
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case TEGRA_VGPU_EVENT_SEMAPHORE_WAKEUP:
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g->ops.semaphore_wakeup(g,
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!!msg->info.sem_wakeup.post_events);
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break;
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case TEGRA_VGPU_EVENT_CHANNEL_CLEANUP:
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vgpu_channel_abort_cleanup(g,
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msg->info.ch_cleanup.chid);
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break;
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case TEGRA_VGPU_EVENT_SET_ERROR_NOTIFIER:
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vgpu_channel_set_error_notifier(g,
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&msg->info.set_error_notifier);
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break;
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default:
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nvgpu_err(g, "unknown event %u", msg->event);
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break;
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}
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vgpu_ivc_release(handle);
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}
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while (!nvgpu_thread_should_stop(&priv->intr_handler)) {
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nvgpu_msleep(10);
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}
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return 0;
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}
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