mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-22 17:36:20 +03:00
123 lines
3.5 KiB
C
123 lines
3.5 KiB
C
/*
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* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/vgpu/vgpu_ivc.h>
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#include <nvgpu/vgpu/tegra_vgpu.h>
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#include <nvgpu/vgpu/vgpu.h>
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#include <nvgpu/gk20a.h>
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#include "perf_vgpu.h"
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#include "common/vgpu/ivc/comm_vgpu.h"
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static int vgpu_sendrecv_perfbuf_cmd(struct gk20a *g, u64 offset, u32 size)
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{
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struct mm_gk20a *mm = &g->mm;
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struct vm_gk20a *vm = mm->perfbuf.vm;
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struct tegra_vgpu_cmd_msg msg;
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struct tegra_vgpu_perfbuf_mgt_params *p =
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&msg.params.perfbuf_management;
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int err;
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msg.cmd = TEGRA_VGPU_CMD_PERFBUF_MGT;
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msg.handle = vgpu_get_handle(g);
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p->vm_handle = vm->handle;
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p->offset = offset;
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p->size = size;
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err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
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err = err ? err : msg.ret;
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return err;
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}
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int vgpu_perfbuffer_enable(struct gk20a *g, u64 offset, u32 size)
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{
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return vgpu_sendrecv_perfbuf_cmd(g, offset, size);
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}
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int vgpu_perfbuffer_disable(struct gk20a *g)
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{
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return vgpu_sendrecv_perfbuf_cmd(g, 0, 0);
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}
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static int vgpu_sendrecv_perfbuf_inst_block_cmd(struct gk20a *g, u32 mode)
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{
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struct mm_gk20a *mm = &g->mm;
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struct vm_gk20a *vm = mm->perfbuf.vm;
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struct tegra_vgpu_cmd_msg msg;
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struct tegra_vgpu_perfbuf_inst_block_mgt_params *p =
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&msg.params.perfbuf_inst_block_management;
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int err;
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msg.cmd = TEGRA_VGPU_CMD_PERFBUF_INST_BLOCK_MGT;
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msg.handle = vgpu_get_handle(g);
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p->vm_handle = vm->handle;
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p->mode = mode;
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err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
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err = err ? err : msg.ret;
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return err;
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}
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int vgpu_perfbuffer_init_inst_block(struct gk20a *g)
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{
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return vgpu_sendrecv_perfbuf_inst_block_cmd(g,
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TEGRA_VGPU_PROF_PERFBUF_INST_BLOCK_INIT);
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}
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void vgpu_perfbuffer_deinit_inst_block(struct gk20a *g)
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{
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vgpu_sendrecv_perfbuf_inst_block_cmd(g,
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TEGRA_VGPU_PROF_PERFBUF_INST_BLOCK_DEINIT);
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}
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int vgpu_perf_update_get_put(struct gk20a *g, u64 bytes_consumed,
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bool update_available_bytes, u64 *put_ptr,
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bool *overflowed)
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{
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struct tegra_vgpu_cmd_msg msg = {};
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struct tegra_vgpu_perf_update_get_put_params *p =
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&msg.params.perf_updat_get_put;
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int err;
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msg.cmd = TEGRA_VGPU_CMD_PERF_UPDATE_GET_PUT;
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msg.handle = vgpu_get_handle(g);
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p->bytes_consumed = bytes_consumed;
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p->update_available_bytes = (u8)update_available_bytes;
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err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
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err = err ? err : msg.ret;
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if (err == 0) {
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if (put_ptr != NULL) {
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*put_ptr = p->put_ptr;
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}
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if (overflowed != NULL) {
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*overflowed = (bool)p->overflowed;
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}
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}
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return err;
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}
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