mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-22 09:12:24 +03:00
78 lines
2.3 KiB
C
78 lines
2.3 KiB
C
/*
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* Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/device.h>
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#include <nvgpu/engines.h>
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#include <nvgpu/log.h>
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#include <nvgpu/errno.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/hw/gm20b/hw_fifo_gm20b.h>
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#include "engines_gm20b.h"
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bool gm20b_is_fault_engine_subid_gpc(struct gk20a *g, u32 engine_subid)
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{
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return (engine_subid == fifo_intr_mmu_fault_info_engine_subid_gpc_v());
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}
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int gm20b_engine_init_ce_info(struct nvgpu_fifo *f)
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{
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struct gk20a *g = f->g;
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u32 i;
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bool found;
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for (i = NVGPU_DEVTYPE_COPY0; i <= NVGPU_DEVTYPE_COPY2; i++) {
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const struct nvgpu_device *dev;
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struct nvgpu_device *dev_rw;
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dev = (struct nvgpu_device *)nvgpu_device_get(g, i,
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i - NVGPU_DEVTYPE_COPY0);
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if (dev == NULL) {
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/*
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* Not an error condition; gm20b has only 1 CE.
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*/
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continue;
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}
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/*
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* Cast to a non-const version since we have to hack up a few fields for
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* SW to work.
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*/
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dev_rw = (struct nvgpu_device *)dev;
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found = g->ops.fifo.find_pbdma_for_runlist(g,
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dev->runlist_id,
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&dev_rw->pbdma_id);
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if (!found) {
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nvgpu_err(g, "busted pbdma map");
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return -EINVAL;
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}
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f->host_engines[dev->engine_id] = dev;
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f->active_engines[f->num_engines] = dev;
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++f->num_engines;
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}
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return 0;
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}
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