mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-22 09:12:24 +03:00
136 lines
3.9 KiB
C
136 lines
3.9 KiB
C
/*
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* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/timers.h>
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#include <nvgpu/log.h>
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#include <nvgpu/io.h>
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#include <nvgpu/fifo.h>
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#include <nvgpu/engines.h>
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#include <nvgpu/device.h>
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#include <hal/fifo/mmu_fault_gm20b.h>
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#include <nvgpu/hw/gm20b/hw_fifo_gm20b.h>
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static const char * const gm20b_gpc_client_descs[] = {
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"l1 0", "t1 0", "pe 0",
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"l1 1", "t1 1", "pe 1",
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"l1 2", "t1 2", "pe 2",
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"l1 3", "t1 3", "pe 3",
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"rast", "gcc", "gpccs",
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"prop 0", "prop 1", "prop 2", "prop 3",
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"l1 4", "t1 4", "pe 4",
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"l1 5", "t1 5", "pe 5",
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"l1 6", "t1 6", "pe 6",
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"l1 7", "t1 7", "pe 7",
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"l1 9", "t1 9", "pe 9",
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"l1 10", "t1 10", "pe 10",
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"l1 11", "t1 11", "pe 11",
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"unknown", "unknown", "unknown", "unknown",
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"tpccs 0", "tpccs 1", "tpccs 2",
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"tpccs 3", "tpccs 4", "tpccs 5",
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"tpccs 6", "tpccs 7", "tpccs 8",
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"tpccs 9", "tpccs 10", "tpccs 11",
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};
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void gm20b_fifo_get_mmu_fault_gpc_desc(struct mmu_fault_info *mmufault)
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{
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if (mmufault->client_id >= ARRAY_SIZE(gm20b_gpc_client_descs)) {
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WARN_ON(mmufault->client_id >=
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ARRAY_SIZE(gm20b_gpc_client_descs));
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} else {
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mmufault->client_id_desc =
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gm20b_gpc_client_descs[mmufault->client_id];
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}
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}
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static inline u32 gm20b_engine_id_to_fault_id(struct gk20a *g,
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u32 engine_id)
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{
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const struct nvgpu_device *dev;
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dev = nvgpu_engine_get_active_eng_info(g, engine_id);
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if (dev == NULL) {
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nvgpu_err(g,
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"engine_id is not in active list/invalid %d",
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engine_id);
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return INVAL_ID;
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}
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return dev->fault_id;
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}
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void gm20b_fifo_trigger_mmu_fault(struct gk20a *g,
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unsigned long engine_ids_bitmask)
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{
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unsigned int poll_delay = POLL_DELAY_MIN_US;
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unsigned long engine_id;
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int ret;
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struct nvgpu_timeout timeout;
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u32 fault_id;
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/* set trigger mmu fault */
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for_each_set_bit(engine_id, &engine_ids_bitmask, 32UL) {
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if (!nvgpu_engine_check_valid_id(g, (u32)engine_id)) {
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nvgpu_err(g, "faulting unknown engine %ld", engine_id);
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continue;
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}
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fault_id = gm20b_engine_id_to_fault_id(g, (u32)engine_id);
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if (fault_id == INVAL_ID) {
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continue;
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}
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nvgpu_writel(g, fifo_trigger_mmu_fault_r(fault_id),
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fifo_trigger_mmu_fault_enable_f(1U));
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}
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ret = nvgpu_timeout_init(g, &timeout, nvgpu_get_poll_timeout(g),
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NVGPU_TIMER_CPU_TIMER);
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if (ret != 0) {
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nvgpu_err(g, "timeout init failed err=%d", ret);
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}
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/* Wait for MMU fault to trigger */
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ret = -EBUSY;
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do {
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if ((nvgpu_readl(g, fifo_intr_0_r()) &
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fifo_intr_0_mmu_fault_pending_f()) != 0U) {
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ret = 0;
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break;
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}
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nvgpu_usleep_range(poll_delay, poll_delay * 2U);
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poll_delay = min_t(u32, poll_delay << 1U, POLL_DELAY_MAX_US);
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} while (nvgpu_timeout_expired(&timeout) == 0);
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if (ret != 0) {
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nvgpu_err(g, "timeout: failed to trigger mmu fault");
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}
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/* release trigger mmu fault */
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for_each_set_bit(engine_id, &engine_ids_bitmask, 32UL) {
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nvgpu_writel(g, fifo_trigger_mmu_fault_r((u32)engine_id), 0U);
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}
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}
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