mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-22 09:12:24 +03:00
91 lines
3.0 KiB
C
91 lines
3.0 KiB
C
/*
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* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/log.h>
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#include <nvgpu/log2.h>
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#include <nvgpu/nvgpu_mem.h>
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#include <nvgpu/io.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/channel.h>
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#include <nvgpu/fifo.h>
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#include "hal/fifo/ramfc_gk20a.h"
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#include "hal/fifo/ramfc_tu104.h"
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#include <nvgpu/hw/tu104/hw_ram_tu104.h>
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int tu104_ramfc_setup(struct nvgpu_channel *ch, u64 gpfifo_base,
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u32 gpfifo_entries, u64 pbdma_acquire_timeout, u32 flags)
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{
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struct gk20a *g = ch->g;
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struct nvgpu_mem *mem = &ch->inst_block;
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u32 data;
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nvgpu_log_fn(g, " ");
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nvgpu_memset(g, mem, 0, 0, ram_fc_size_val_v());
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nvgpu_mem_wr32(g, mem, ram_fc_gp_base_w(),
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g->ops.pbdma.get_gp_base(gpfifo_base));
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nvgpu_mem_wr32(g, mem, ram_fc_gp_base_hi_w(),
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g->ops.pbdma.get_gp_base_hi(gpfifo_base, gpfifo_entries));
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nvgpu_mem_wr32(g, mem, ram_fc_signature_w(),
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g->ops.pbdma.get_signature(g));
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nvgpu_mem_wr32(g, mem, ram_fc_pb_header_w(),
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g->ops.pbdma.get_fc_pb_header());
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nvgpu_mem_wr32(g, mem, ram_fc_subdevice_w(),
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g->ops.pbdma.get_fc_subdevice());
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nvgpu_mem_wr32(g, mem, ram_fc_target_w(),
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g->ops.pbdma.get_fc_target(NULL));
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nvgpu_mem_wr32(g, mem, ram_fc_acquire_w(),
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g->ops.pbdma.acquire_val(pbdma_acquire_timeout));
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nvgpu_mem_wr32(g, mem, ram_fc_set_channel_info_w(),
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g->ops.pbdma.set_channel_info_veid(ch->subctx_id));
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nvgpu_mem_wr32(g, mem, ram_in_engine_wfi_veid_w(),
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ram_in_engine_wfi_veid_f(ch->subctx_id));
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if (ch->is_privileged_channel) {
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/* Set privilege level for channel */
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nvgpu_mem_wr32(g, mem, ram_fc_config_w(),
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g->ops.pbdma.get_config_auth_level_privileged());
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/* Enable HCE priv mode for phys mode transfer */
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nvgpu_mem_wr32(g, mem, ram_fc_hce_ctrl_w(),
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g->ops.pbdma.get_ctrl_hce_priv_mode_yes());
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}
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/* Enable userd writeback */
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data = nvgpu_mem_rd32(g, mem, ram_fc_config_w());
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data = g->ops.pbdma.config_userd_writeback_enable(data);
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nvgpu_mem_wr32(g, mem, ram_fc_config_w(), data);
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return g->ops.ramfc.commit_userd(ch);
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}
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