mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-22 09:12:24 +03:00
115 lines
3.8 KiB
C
115 lines
3.8 KiB
C
/*
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* Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/dma.h>
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#include <nvgpu/nvgpu_mem.h>
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#include <nvgpu/types.h>
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#include <nvgpu/io.h>
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#include <nvgpu/gk20a.h>
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#include "ramin_tu104.h"
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#include <nvgpu/hw/tu104/hw_ram_tu104.h>
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int tu104_ramin_init_pdb_cache_errata(struct gk20a *g)
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{
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u32 size = NVGPU_CPU_PAGE_SIZE * 258U;
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u64 last_bind_pdb_addr;
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u64 pdb_addr;
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u32 pdb_addr_lo, pdb_addr_hi;
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u32 i;
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int err;
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if (nvgpu_mem_is_valid(&g->pdb_cache_errata_mem)) {
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return 0;
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}
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/*
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* Allocate memory for 257 instance block binds +
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* PDB bound to 257th instance block
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*/
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err = nvgpu_dma_alloc_sys(g, size, &g->pdb_cache_errata_mem);
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if (err != 0) {
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return err;
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}
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/*
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* 257th instance block (i.e. last bind) needs to be bound to
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* valid memory
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* First 256 binds can happen to dummy addresses
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*/
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pdb_addr = NVGPU_CPU_PAGE_SIZE;
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last_bind_pdb_addr = nvgpu_mem_get_addr(g, &g->pdb_cache_errata_mem) +
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(257U * NVGPU_CPU_PAGE_SIZE);
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/* Setup first 256 instance blocks */
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for (i = 0U; i < 256U; i++) {
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pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v());
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pdb_addr_hi = u64_hi32(pdb_addr);
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nvgpu_mem_wr32(g, &g->pdb_cache_errata_mem,
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ram_in_page_dir_base_lo_w() + (i * NVGPU_CPU_PAGE_SIZE / 4U),
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nvgpu_aperture_mask(g, &g->pdb_cache_errata_mem,
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ram_in_page_dir_base_target_sys_mem_ncoh_f(),
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ram_in_page_dir_base_target_sys_mem_coh_f(),
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ram_in_page_dir_base_target_vid_mem_f()) |
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ram_in_page_dir_base_vol_true_f() |
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ram_in_big_page_size_64kb_f() |
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ram_in_page_dir_base_lo_f(pdb_addr_lo) |
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ram_in_use_ver2_pt_format_true_f());
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nvgpu_mem_wr32(g, &g->pdb_cache_errata_mem,
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ram_in_page_dir_base_hi_w() + (i * NVGPU_CPU_PAGE_SIZE / 4U),
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ram_in_page_dir_base_hi_f(pdb_addr_hi));
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pdb_addr += NVGPU_CPU_PAGE_SIZE;
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}
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/* Setup 257th instance block */
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pdb_addr_lo = u64_lo32(last_bind_pdb_addr >> ram_in_base_shift_v());
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pdb_addr_hi = u64_hi32(last_bind_pdb_addr);
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nvgpu_mem_wr32(g, &g->pdb_cache_errata_mem,
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ram_in_page_dir_base_lo_w() + (256U * NVGPU_CPU_PAGE_SIZE / 4U),
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nvgpu_aperture_mask(g, &g->pdb_cache_errata_mem,
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ram_in_page_dir_base_target_sys_mem_ncoh_f(),
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ram_in_page_dir_base_target_sys_mem_coh_f(),
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ram_in_page_dir_base_target_vid_mem_f()) |
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ram_in_page_dir_base_vol_true_f() |
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ram_in_big_page_size_64kb_f() |
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ram_in_page_dir_base_lo_f(pdb_addr_lo) |
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ram_in_use_ver2_pt_format_true_f());
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nvgpu_mem_wr32(g, &g->pdb_cache_errata_mem,
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ram_in_page_dir_base_hi_w() + (256U * NVGPU_CPU_PAGE_SIZE / 4U),
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ram_in_page_dir_base_hi_f(pdb_addr_hi));
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return 0;
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}
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void tu104_ramin_deinit_pdb_cache_errata(struct gk20a *g)
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{
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if (nvgpu_mem_is_valid(&g->pdb_cache_errata_mem)) {
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nvgpu_dma_free(g, &g->pdb_cache_errata_mem);
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}
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}
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