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git://nv-tegra.nvidia.com/linux-nvgpu.git
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66 lines
2.6 KiB
C
66 lines
2.6 KiB
C
/*
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* Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_MC_GM20B_H
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#define NVGPU_MC_GM20B_H
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#include <nvgpu/types.h>
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struct gk20a;
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struct nvgpu_device;
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u32 gm20b_get_chip_details(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev);
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u32 gm20b_mc_isr_nonstall(struct gk20a *g);
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int gm20b_mc_enable_units(struct gk20a *g, u32 units, bool enable);
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int gm20b_mc_enable_dev(struct gk20a *g, const struct nvgpu_device *dev,
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bool enable);
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int gm20b_mc_enable_devtype(struct gk20a *g, u32 devtype, bool enable);
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#ifdef CONFIG_NVGPU_LS_PMU
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bool gm20b_mc_is_enabled(struct gk20a *g, u32 unit);
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#endif
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#ifdef CONFIG_NVGPU_HAL_NON_FUSA
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void gm20b_mc_intr_mask(struct gk20a *g);
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void gm20b_mc_intr_enable(struct gk20a *g);
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void gm20b_mc_intr_stall_unit_config(struct gk20a *g, u32 unit,
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bool enable);
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void gm20b_mc_intr_nonstall_unit_config(struct gk20a *g, u32 unit,
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bool enable);
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void gm20b_mc_isr_stall(struct gk20a *g);
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u32 gm20b_mc_intr_stall(struct gk20a *g);
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void gm20b_mc_intr_stall_pause(struct gk20a *g);
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void gm20b_mc_intr_stall_resume(struct gk20a *g);
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u32 gm20b_mc_intr_nonstall(struct gk20a *g);
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void gm20b_mc_intr_nonstall_pause(struct gk20a *g);
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void gm20b_mc_intr_nonstall_resume(struct gk20a *g);
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bool gm20b_mc_is_intr1_pending(struct gk20a *g, u32 unit, u32 mc_intr_1);
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void gm20b_mc_log_pending_intrs(struct gk20a *g);
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void gm20b_mc_fb_reset(struct gk20a *g);
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void gm20b_mc_ltc_isr(struct gk20a *g);
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bool gm20b_mc_is_mmu_fault_pending(struct gk20a *g);
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#endif
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#endif /* NVGPU_MC_GM20B_H */
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