mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
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123 lines
5.1 KiB
C
123 lines
5.1 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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struct gk20a;
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struct unit_module;
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/** @addtogroup SWUTS-cg
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* @{
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*
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* Software Unit Test Specification for cg
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*/
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/**
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* Test specification for: test_cg
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*
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* Description: The cg unit shall be able to setup the clock gating register
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* values as specified in the hal reglist structures for BLCG/SLCG.
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*
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* Test Type: Feature
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*
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* Targets: nvgpu_cg_blcg_fb_ltc_load_enable, nvgpu_cg_blcg_fifo_load_enable,
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* nvgpu_cg_blcg_ce_load_enable, nvgpu_cg_blcg_pmu_load_enable,
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* nvgpu_cg_blcg_gr_load_enable, nvgpu_cg_slcg_fb_ltc_load_enable,
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* nvgpu_cg_slcg_priring_load_enable, nvgpu_cg_slcg_fifo_load_enable,
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* nvgpu_cg_slcg_pmu_load_enable, nvgpu_cg_slcg_therm_load_enable,
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* nvgpu_cg_slcg_ce2_load_enable, nvgpu_cg_init_gr_load_gating_prod
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*
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* Input: The struct specifying type of clock gating, target nvgpu routine
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* that handles the setup, clock gating domain descriptors.
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*
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* Steps:
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* - Initialize the test environment:
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* - Register read/write IO callbacks.
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* - Add relevant fuse registers to the register space.
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* - Initialize hal to setup the hal functions.
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* - Initialize slcg and blcg gating register data by querying through
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* nvgpu exported functions.
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* - Add the domain gating registers to the register space.
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* - Load invalid values in the gating registers.
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* - Invoke the nvgpu function to load the clock gating values.
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* - Verify that load is not enabled as BLCG/SLCG enabled flag isn't set.
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* - Enable BLCG/SLCG enabled flag.
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* - Invoke the nvgpu function to load the clock gating values.
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* - Verify that load is not enabled as platform capability isn't set.
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* - Disable BLCG/SLCG enabled flag.
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* - Set the platform capability.
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* - Invoke the nvgpu function to load the clock gating values.
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* - Verify that load is not enabled as enabled flag isn't set.
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* - Enable BLCG/SLCG enabled flag.
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* - Invoke the nvgpu function to load the clock gating values.
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* - Verify that load is enabled.
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* - Invoke the nvgpu functions to load the non-prod clock gating values.
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* - Verify that load is not enabled.
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* - Set all CG gpu_ops to NULL.
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* - Invoke the nvgpu function to load the clock gating values.
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* - Verify that load is not enabled as HALs are not set.
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* - Restore the CG gpu_ops.
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* - Any invalid accesses by nvgpu will be caught through ABORTs and
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* test fails if ABORTs are encountered.
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* - Delete domain gating registers from the registere space.
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*
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* Output: Returns PASS if the steps above were executed successfully. FAIL
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* otherwise.
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*/
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int test_cg(struct unit_module *m, struct gk20a *g, void *args);
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/**
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* Test specification for: test_elcg
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*
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* Description: The cg unit shall be able to setup the engine therm register
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* values to enable/disable ELCG.
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*
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* Test Type: Feature
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*
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* Targets: nvgpu_cg_elcg_enable_no_wait, nvgpu_cg_elcg_disable_no_wait
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*
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* Input: None
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*
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* Steps:
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* - Initialize the test environment:
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* - Register read/write IO callbacks.
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* - Add relevant fuse registers to the register space.
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* - Initialize hal to setup the hal functions.
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* - Initialize fifo support to configure ELCG at engine level.
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* - Add the engine therm registers to the register space.
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* - Invoke the nvgpu function to enable/disable ELCG.
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* - Verify that cg mode isn't set in therm registers as ELCG enabled flag
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* isn't set.
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* - Enable ELCG enabled flag.
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* - Invoke the nvgpu function to enable/disable ELCG.
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* - Verify that cg mode isn't set in therm registers as ELCG platform
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* capability isn't set.
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* - Set the platform capability.
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* - Invoke the nvgpu function to enable/disable ELCG.
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* - Verify that cg mode is set in therm registers.
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* - Any invalid accesses by nvgpu will be caught through ABORTs and
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* test fails if ABORTs are encountered.
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* - Delete engine therm registers from the registere space.
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*
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* Output: Returns PASS if the steps above were executed successfully. FAIL
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* otherwise.
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*/
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int test_elcg(struct unit_module *m, struct gk20a *g, void *args);
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