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38 lines
1.5 KiB
C
38 lines
1.5 KiB
C
/*
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* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __UNIT_NVGPU_FUSE_PRIV_H__
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#define __UNIT_NVGPU_FUSE_PRIV_H__
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extern u32 gcplex_config;
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int read_gcplex_config_fuse_pass(struct gk20a *g, u32 *val);
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int read_gcplex_config_fuse_fail(struct gk20a *g, u32 *val);
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struct fuse_test_args {
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u32 gpu_arch;
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u32 gpu_impl;
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u32 fuse_base_addr;
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u32 sec_fuse_addr;
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};
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#endif /* __UNIT_NVGPU_FUSE_PRIV_H__ */
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