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0090ee5aca
The last major item preventing the core MM code in the nvgpu driver from being platform agnostic is the usage of Linux scattergather tables and scattergather lists. These data structures are used throughout the mapping code to handle discontiguous DMA allocations and also overloaded to represent VIDMEM allocs. The notion of a scatter gather table is crucial to a HW device that can handle discontiguous DMA. The GPU has a MMU which allows the GPU to do page gathering and present a virtually contiguous buffer to the GPU HW. As a result it makes sense for the GPU driver to use some sort of scatter gather concept so maximize memory usage efficiency. To that end this patch keeps the notion of a scatter gather list but implements it in the nvgpu common code. It is based heavily on the Linux SGL concept. It is a singly linked list of blocks - each representing a chunk of memory. To map or use a DMA allocation SW must iterate over each block in the SGL. This patch implements the most basic level of support for this data structure. There are certainly easy optimizations that could be done to speed up the current implementation. However, this patches' goal is to simply divest the core MM code from any last Linux'isms. Speed and efficiency come next. Change-Id: Icf44641db22d87fa1d003debbd9f71b605258e42 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1530867 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
134 lines
3.2 KiB
C
134 lines
3.2 KiB
C
/*
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <nvgpu/pramin.h>
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#include <nvgpu/page_allocator.h>
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#include "gk20a/gk20a.h"
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/*
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* Flip this to force all gk20a_mem* accesses via PRAMIN from the start of the
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* boot, even for buffers that would work via cpu_va. In runtime, the flag is
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* in debugfs, called "force_pramin".
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*/
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#define GK20A_FORCE_PRAMIN_DEFAULT false
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void pramin_access_batch_rd_n(struct gk20a *g, u32 start, u32 words, u32 **arg)
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{
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u32 r = start, *dest_u32 = *arg;
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if (!g->regs) {
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__gk20a_warn_on_no_regs();
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return;
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}
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while (words--) {
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*dest_u32++ = gk20a_readl(g, r);
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r += sizeof(u32);
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}
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*arg = dest_u32;
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}
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void pramin_access_batch_wr_n(struct gk20a *g, u32 start, u32 words, u32 **arg)
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{
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u32 r = start, *src_u32 = *arg;
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if (!g->regs) {
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__gk20a_warn_on_no_regs();
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return;
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}
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while (words--) {
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writel_relaxed(*src_u32++, g->regs + r);
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r += sizeof(u32);
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}
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*arg = src_u32;
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}
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void pramin_access_batch_set(struct gk20a *g, u32 start, u32 words, u32 **arg)
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{
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u32 r = start, repeat = **arg;
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if (!g->regs) {
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__gk20a_warn_on_no_regs();
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return;
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}
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while (words--) {
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writel_relaxed(repeat, g->regs + r);
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r += sizeof(u32);
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}
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}
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/*
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* The PRAMIN range is 1 MB, must change base addr if a buffer crosses that.
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* This same loop is used for read/write/memset. Offset and size in bytes.
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* One call to "loop" is done per range, with "arg" supplied.
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*/
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void nvgpu_pramin_access_batched(struct gk20a *g, struct nvgpu_mem *mem,
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u32 offset, u32 size, pramin_access_batch_fn loop, u32 **arg)
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{
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struct nvgpu_page_alloc *alloc = NULL;
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struct nvgpu_mem_sgl *sgl;
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u32 byteoff, start_reg, until_end, n;
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alloc = get_vidmem_page_alloc(mem->priv.sgt->sgl);
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sgl = alloc->sgl;
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while (sgl) {
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if (offset >= nvgpu_mem_sgl_length(sgl)) {
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offset -= nvgpu_mem_sgl_length(sgl);
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sgl = sgl->next;
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} else {
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break;
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}
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}
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while (size) {
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u32 sgl_len = (u32)nvgpu_mem_sgl_length(sgl);
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byteoff = g->ops.pramin.enter(g, mem, sgl,
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offset / sizeof(u32));
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start_reg = g->ops.pramin.data032_r(byteoff / sizeof(u32));
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until_end = SZ_1M - (byteoff & (SZ_1M - 1));
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n = min3(size, until_end, (u32)(sgl_len - offset));
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loop(g, start_reg, n / sizeof(u32), arg);
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/* read back to synchronize accesses */
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gk20a_readl(g, start_reg);
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g->ops.pramin.exit(g, mem, sgl);
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size -= n;
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if (n == (sgl_len - offset)) {
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sgl = nvgpu_mem_sgl_next(sgl);
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offset = 0;
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} else {
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offset += n;
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}
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}
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}
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void nvgpu_init_pramin(struct mm_gk20a *mm)
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{
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mm->pramin_window = 0;
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nvgpu_spinlock_init(&mm->pramin_window_lock);
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mm->force_pramin = GK20A_FORCE_PRAMIN_DEFAULT;
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}
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