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gk20a_fifo_recover_tsg does high-level software calls and invokes gk20a_fifo_recover. This function belongs to the tsg unit and is moved to tsg.c file. Also, the function is renamed to nvgpu_tsg_recover. Jira NVGPU-1237 Change-Id: Id1911fb182817b0cfc47b3219065cba6c4ca507a Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1970034 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
144 lines
4.4 KiB
C
144 lines
4.4 KiB
C
/*
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* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef TSG_GK20A_H
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#define TSG_GK20A_H
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#include <nvgpu/lock.h>
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#include <nvgpu/kref.h>
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#include <nvgpu/rwsem.h>
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#include <nvgpu/list.h>
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#include <nvgpu/cond.h>
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#define NVGPU_INVALID_TSG_ID (U32_MAX)
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struct gk20a;
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struct channel_gk20a;
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struct nvgpu_gr_ctx;
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struct nvgpu_tsg_sm_error_state {
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u32 hww_global_esr;
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u32 hww_warp_esr;
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u64 hww_warp_esr_pc;
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u32 hww_global_esr_report_mask;
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u32 hww_warp_esr_report_mask;
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};
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struct tsg_gk20a {
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struct gk20a *g;
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struct vm_gk20a *vm;
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struct nvgpu_mem *eng_method_buffers;
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struct nvgpu_gr_ctx *gr_ctx;
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struct nvgpu_ref refcount;
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struct nvgpu_list_node ch_list;
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struct nvgpu_list_node event_id_list;
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struct nvgpu_rwsem ch_list_lock;
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struct nvgpu_mutex event_id_list_lock;
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u32 num_active_channels;
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unsigned int timeslice_us;
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unsigned int timeslice_timeout;
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unsigned int timeslice_scale;
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u32 interleave_level;
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u32 tsgid;
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u32 runlist_id;
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pid_t tgid;
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u32 num_active_tpcs;
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u8 tpc_pg_enabled;
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bool tpc_num_initialized;
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bool in_use;
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struct nvgpu_tsg_sm_error_state *sm_error_states;
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#define NVGPU_SM_EXCEPTION_TYPE_MASK_NONE (0x0U)
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#define NVGPU_SM_EXCEPTION_TYPE_MASK_FATAL (0x1U << 0)
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u32 sm_exception_mask_type;
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struct nvgpu_mutex sm_exception_mask_lock;
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};
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bool gk20a_is_channel_marked_as_tsg(struct channel_gk20a *ch);
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int gk20a_tsg_open_common(struct gk20a *g, struct tsg_gk20a *tsg);
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struct tsg_gk20a *gk20a_tsg_open(struct gk20a *g, pid_t pid);
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void gk20a_tsg_release_common(struct gk20a *g, struct tsg_gk20a *tsg);
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void gk20a_tsg_release(struct nvgpu_ref *ref);
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int gk20a_init_tsg_support(struct gk20a *g, u32 tsgid);
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struct tsg_gk20a *tsg_gk20a_from_ch(struct channel_gk20a *ch);
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int gk20a_enable_tsg(struct tsg_gk20a *tsg);
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int gk20a_disable_tsg(struct tsg_gk20a *tsg);
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int gk20a_tsg_bind_channel(struct tsg_gk20a *tsg,
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struct channel_gk20a *ch);
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int gk20a_tsg_unbind_channel(struct channel_gk20a *ch);
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void nvgpu_tsg_recover(struct gk20a *g, struct tsg_gk20a *tsg,
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bool verbose, u32 rc_type);
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void nvgpu_tsg_set_ctx_mmu_error(struct gk20a *g,
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struct tsg_gk20a *tsg);
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bool nvgpu_tsg_mark_error(struct gk20a *g, struct tsg_gk20a *tsg);
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void gk20a_tsg_event_id_post_event(struct tsg_gk20a *tsg,
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int event_id);
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bool nvgpu_tsg_check_ctxsw_timeout(struct tsg_gk20a *tsg,
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bool *verbose, u32 *ms);
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int gk20a_tsg_set_runlist_interleave(struct tsg_gk20a *tsg, u32 level);
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int gk20a_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice);
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u32 gk20a_tsg_get_timeslice(struct tsg_gk20a *tsg);
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int gk20a_tsg_set_priority(struct gk20a *g, struct tsg_gk20a *tsg,
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u32 priority);
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int gk20a_tsg_alloc_sm_error_states_mem(struct gk20a *g,
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struct tsg_gk20a *tsg,
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u32 num_sm);
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void gk20a_tsg_update_sm_error_state_locked(struct tsg_gk20a *tsg,
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u32 sm_id,
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struct nvgpu_tsg_sm_error_state *sm_error_state);
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int gk20a_tsg_set_sm_exception_type_mask(struct channel_gk20a *ch,
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u32 exception_mask);
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struct gk20a_event_id_data {
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struct gk20a *g;
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int id; /* ch or tsg */
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int pid;
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u32 event_id;
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bool event_posted;
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struct nvgpu_cond event_id_wq;
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struct nvgpu_mutex lock;
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struct nvgpu_list_node event_id_node;
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};
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static inline struct gk20a_event_id_data *
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gk20a_event_id_data_from_event_id_node(struct nvgpu_list_node *node)
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{
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return (struct gk20a_event_id_data *)
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((uintptr_t)node - offsetof(struct gk20a_event_id_data, event_id_node));
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};
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#endif /* TSG_GK20A_H */
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