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MISRA Rule 10.4 only allows the usage of arithmetic operations on operands of the same essential type category. Adding "U" at the end of the integer literals to have same type of operands when an arithmetic operation is performed. This fixes violation where an arithmetic operation is performed on signed and unsigned int types. JIRA NVGPU-992 Change-Id: Icb724f3424c8161c12b69d373ff08c7648f79e56 Signed-off-by: Sai Nikhil <snikhil@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1834225 GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
260 lines
7.6 KiB
C
260 lines
7.6 KiB
C
/*
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/bios.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
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#include <nvgpu/boardobjgrp.h>
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#include <nvgpu/boardobjgrp_e32.h>
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#include <nvgpu/string.h>
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#include "thrmchannel.h"
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#include "thrm.h"
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#include "gp106/bios_gp106.h"
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static int _therm_channel_pmudatainit_device(struct gk20a *g,
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struct boardobj *board_obj_ptr,
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struct nv_pmu_boardobj *ppmudata)
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{
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int status = 0;
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struct therm_channel *pchannel;
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struct therm_channel_device *ptherm_channel;
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struct nv_pmu_therm_therm_channel_device_boardobj_set *pset;
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status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata);
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if (status != 0) {
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nvgpu_err(g,
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"error updating pmu boardobjgrp for therm channel 0x%x",
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status);
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status = -ENOMEM;
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goto done;
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}
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pchannel = (struct therm_channel *)board_obj_ptr;
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pset = (struct nv_pmu_therm_therm_channel_device_boardobj_set *)ppmudata;
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ptherm_channel = (struct therm_channel_device *)board_obj_ptr;
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pset->super.scaling = pchannel->scaling;
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pset->super.offset = pchannel->offset;
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pset->super.temp_min = pchannel->temp_min;
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pset->super.temp_max = pchannel->temp_max;
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pset->therm_dev_idx = ptherm_channel->therm_dev_idx;
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pset->therm_dev_prov_idx = ptherm_channel->therm_dev_prov_idx;
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done:
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return status;
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}
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static struct boardobj *construct_channel_device(struct gk20a *g,
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void *pargs, u16 pargs_size, u8 type)
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{
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struct boardobj *board_obj_ptr = NULL;
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struct therm_channel *pchannel;
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struct therm_channel_device *pchannel_device;
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int status;
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u16 scale_shift = BIT16(8);
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struct therm_channel_device *therm_device = (struct therm_channel_device*)pargs;
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status = boardobj_construct_super(g, &board_obj_ptr,
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pargs_size, pargs);
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if (status != 0) {
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return NULL;
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}
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/* Set Super class interfaces */
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board_obj_ptr->pmudatainit = _therm_channel_pmudatainit_device;
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pchannel = (struct therm_channel *)board_obj_ptr;
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pchannel_device = (struct therm_channel_device *)board_obj_ptr;
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g->ops.therm.get_internal_sensor_limits(&pchannel->temp_max,
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&pchannel->temp_min);
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pchannel->scaling = S16(scale_shift);
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pchannel->offset = 0;
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pchannel_device->therm_dev_idx = therm_device->therm_dev_idx;
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pchannel_device->therm_dev_prov_idx = therm_device->therm_dev_prov_idx;
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nvgpu_log_info(g, " Done");
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return board_obj_ptr;
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}
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static int _therm_channel_pmudata_instget(struct gk20a *g,
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struct nv_pmu_boardobjgrp *pmuboardobjgrp,
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struct nv_pmu_boardobj **ppboardobjpmudata,
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u8 idx)
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{
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struct nv_pmu_therm_therm_channel_boardobj_grp_set *pgrp_set =
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(struct nv_pmu_therm_therm_channel_boardobj_grp_set *)
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pmuboardobjgrp;
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nvgpu_log_info(g, " ");
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/*check whether pmuboardobjgrp has a valid boardobj in index*/
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if (((u32)BIT(idx) &
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pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0U) {
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return -EINVAL;
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}
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*ppboardobjpmudata = (struct nv_pmu_boardobj *)
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&pgrp_set->objects[idx].data.board_obj;
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nvgpu_log_info(g, " Done");
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return 0;
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}
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static int devinit_get_therm_channel_table(struct gk20a *g,
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struct therm_channels *pthermchannelobjs)
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{
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int status = 0;
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u8 *therm_channel_table_ptr = NULL;
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u8 *curr_therm_channel_table_ptr = NULL;
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struct boardobj *boardobj;
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struct therm_channel_1x_header therm_channel_table_header = { 0 };
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struct therm_channel_1x_entry *therm_channel_table_entry = NULL;
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u32 index;
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u32 obj_index = 0;
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u16 therm_channel_size = 0;
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union {
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struct boardobj boardobj;
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struct therm_channel therm_channel;
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struct therm_channel_device device;
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} therm_channel_data;
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nvgpu_log_info(g, " ");
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therm_channel_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
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g->bios.perf_token, THERMAL_CHANNEL_TABLE);
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if (therm_channel_table_ptr == NULL) {
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status = -EINVAL;
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goto done;
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}
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nvgpu_memcpy((u8 *)&therm_channel_table_header, therm_channel_table_ptr,
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VBIOS_THERM_CHANNEL_1X_HEADER_SIZE_09);
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if (therm_channel_table_header.version !=
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VBIOS_THERM_CHANNEL_VERSION_1X) {
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status = -EINVAL;
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goto done;
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}
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if (therm_channel_table_header.header_size <
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VBIOS_THERM_CHANNEL_1X_HEADER_SIZE_09) {
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status = -EINVAL;
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goto done;
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}
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curr_therm_channel_table_ptr = (therm_channel_table_ptr +
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VBIOS_THERM_CHANNEL_1X_HEADER_SIZE_09);
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for (index = 0; index < therm_channel_table_header.num_table_entries;
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index++) {
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therm_channel_table_entry = (struct therm_channel_1x_entry *)
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(curr_therm_channel_table_ptr +
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(therm_channel_table_header.table_entry_size * index));
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if (therm_channel_table_entry->class_id !=
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NV_VBIOS_THERM_CHANNEL_1X_ENTRY_CLASS_DEVICE) {
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continue;
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}
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therm_channel_data.device.therm_dev_idx = therm_channel_table_entry->param0;
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therm_channel_data.device.therm_dev_prov_idx = therm_channel_table_entry->param1;
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therm_channel_size = sizeof(struct therm_channel_device);
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therm_channel_data.boardobj.type = CTRL_THERMAL_THERM_CHANNEL_CLASS_DEVICE;
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boardobj = construct_channel_device(g, &therm_channel_data,
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therm_channel_size, therm_channel_data.boardobj.type);
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if (boardobj == NULL) {
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nvgpu_err(g,
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"unable to create thermal device for %d type %d",
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index, therm_channel_data.boardobj.type);
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status = -EINVAL;
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goto done;
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}
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status = boardobjgrp_objinsert(&pthermchannelobjs->super.super,
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boardobj, obj_index);
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if (status != 0) {
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nvgpu_err(g,
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"unable to insert thermal device boardobj for %d", index);
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status = -EINVAL;
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goto done;
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}
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++obj_index;
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}
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done:
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nvgpu_log_info(g, " done status %x", status);
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return status;
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}
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int therm_channel_sw_setup(struct gk20a *g)
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{
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int status;
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struct boardobjgrp *pboardobjgrp = NULL;
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struct therm_channels *pthermchannelobjs;
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/* Construct the Super Class and override the Interfaces */
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status = boardobjgrpconstruct_e32(g,
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&g->therm_pmu->therm_channelobjs.super);
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if (status != 0) {
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nvgpu_err(g,
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"error creating boardobjgrp for therm devices, status - 0x%x",
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status);
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goto done;
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}
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pboardobjgrp = &g->therm_pmu->therm_channelobjs.super.super;
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pthermchannelobjs = &(g->therm_pmu->therm_channelobjs);
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/* Override the Interfaces */
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pboardobjgrp->pmudatainstget = _therm_channel_pmudata_instget;
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status = devinit_get_therm_channel_table(g, pthermchannelobjs);
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if (status != 0) {
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goto done;
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}
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BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, THERM, THERM_CHANNEL);
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status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp,
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therm, THERM, therm_channel, THERM_CHANNEL);
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if (status != 0) {
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nvgpu_err(g,
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"error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x",
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status);
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goto done;
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}
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done:
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nvgpu_log_info(g, " done status %x", status);
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return status;
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}
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