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5366778e8e
MISRA rule 21.2 doesn't allow the use of macro names which start with an underscore. These leading underscores are to be removed from the macro names. This patch will fix such violations in the include directory by renaming them to follow the convention, 'NVGPU_PARENT-DIR_HEADER_H'. JIRA NVGPU-1028 Change-Id: I14e3558c80511314e32ef79c2b609a9fd9cf0a44 Signed-off-by: smadhavan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813123 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
113 lines
4.1 KiB
C
113 lines
4.1 KiB
C
/*
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* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_NVHOST_H
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#define NVGPU_NVHOST_H
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#ifdef CONFIG_TEGRA_GK20A_NVHOST
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#include <nvgpu/types.h>
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struct nvgpu_nvhost_dev;
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struct gk20a;
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struct sync_pt;
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struct sync_fence;
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struct timespec;
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int nvgpu_get_nvhost_dev(struct gk20a *g);
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void nvgpu_free_nvhost_dev(struct gk20a *g);
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int nvgpu_nvhost_module_busy_ext(struct nvgpu_nvhost_dev *nvhost_dev);
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void nvgpu_nvhost_module_idle_ext(struct nvgpu_nvhost_dev *nvhost_dev);
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void nvgpu_nvhost_debug_dump_device(struct nvgpu_nvhost_dev *nvhost_dev);
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int nvgpu_nvhost_syncpt_is_expired_ext(struct nvgpu_nvhost_dev *nvhost_dev,
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u32 id, u32 thresh);
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int nvgpu_nvhost_syncpt_wait_timeout_ext(struct nvgpu_nvhost_dev *nvhost_dev,
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u32 id, u32 thresh, u32 timeout, u32 *value, struct timespec *ts);
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u32 nvgpu_nvhost_syncpt_incr_max_ext(struct nvgpu_nvhost_dev *nvhost_dev,
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u32 id, u32 incrs);
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void nvgpu_nvhost_syncpt_set_min_eq_max_ext(struct nvgpu_nvhost_dev *nvhost_dev,
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u32 id);
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int nvgpu_nvhost_syncpt_read_ext_check(struct nvgpu_nvhost_dev *nvhost_dev,
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u32 id, u32 *val);
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u32 nvgpu_nvhost_syncpt_read_maxval(struct nvgpu_nvhost_dev *nvhost_dev,
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u32 id);
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void nvgpu_nvhost_syncpt_set_safe_state(
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struct nvgpu_nvhost_dev *nvhost_dev, u32 id);
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int nvgpu_nvhost_intr_register_notifier(struct nvgpu_nvhost_dev *nvhost_dev,
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u32 id, u32 thresh, void (*callback)(void *, int), void *private_data);
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const char *nvgpu_nvhost_syncpt_get_name(struct nvgpu_nvhost_dev *nvhost_dev,
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int id);
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bool nvgpu_nvhost_syncpt_is_valid_pt_ext(struct nvgpu_nvhost_dev *nvhost_dev,
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u32 id);
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void nvgpu_nvhost_syncpt_put_ref_ext(struct nvgpu_nvhost_dev *nvhost_dev,
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u32 id);
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u32 nvgpu_nvhost_get_syncpt_host_managed(struct nvgpu_nvhost_dev *nvhost_dev,
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u32 param,
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const char *syncpt_name);
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u32 nvgpu_nvhost_get_syncpt_client_managed(struct nvgpu_nvhost_dev *nvhost_dev,
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const char *syncpt_name);
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int nvgpu_nvhost_create_symlink(struct gk20a *g);
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void nvgpu_nvhost_remove_symlink(struct gk20a *g);
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#ifdef CONFIG_SYNC
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u32 nvgpu_nvhost_sync_pt_id(struct sync_pt *pt);
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u32 nvgpu_nvhost_sync_pt_thresh(struct sync_pt *pt);
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int nvgpu_nvhost_sync_num_pts(struct sync_fence *fence);
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struct sync_fence *nvgpu_nvhost_sync_fdget(int fd);
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struct sync_fence *nvgpu_nvhost_sync_create_fence(
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struct nvgpu_nvhost_dev *nvhost_dev,
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u32 id, u32 thresh, const char *name);
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#endif /* CONFIG_SYNC */
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#ifdef CONFIG_TEGRA_T19X_GRHOST
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int nvgpu_nvhost_syncpt_unit_interface_get_aperture(
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struct nvgpu_nvhost_dev *nvhost_dev,
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u64 *base, size_t *size);
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u32 nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(u32 syncpt_id);
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int nvgpu_nvhost_syncpt_init(struct gk20a *g);
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#else
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static inline int nvgpu_nvhost_syncpt_unit_interface_get_aperture(
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struct nvgpu_nvhost_dev *nvhost_dev,
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u64 *base, size_t *size)
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{
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return -EINVAL;
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}
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static inline u32 nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(u32 syncpt_id)
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{
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return 0;
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}
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static inline int nvgpu_nvhost_syncpt_init(struct gk20a *g)
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{
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return 0;
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}
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#endif
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#endif /* CONFIG_TEGRA_GK20A_NVHOST */
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#endif /* NVGPU_NVHOST_H */
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