mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-22 09:12:24 +03:00
01eb416745
Changes 1. Remove dGPU flag dependency on calling gsp sw init on tot. 2. Created Enable flag for gsp scheduler to enable them on ga10b platforms. 3. Engine config flag is only enabled for dGPU enabled platforms, as gsp is using engine functions it need to be enabled for all gsp sched enabled builds. 4. Changes in gsp_sequence_init/de_init where on qnx we are seeing issues. NVGPU-9297 Change-Id: Ia4bce85ae8fd2794da1553e9ea418c76845a10ac Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2822537 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
132 lines
3.4 KiB
C
132 lines
3.4 KiB
C
/*
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* Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/firmware.h>
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#include <nvgpu/falcon.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/log.h>
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#include <nvgpu/gsp.h>
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#ifdef CONFIG_NVGPU_GSP_STRESS_TEST
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#include <nvgpu/gsp/gsp_test.h>
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#endif
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#ifdef CONFIG_NVGPU_GSP_SCHEDULER
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#include <nvgpu/gsp_sched.h>
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#endif
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void nvgpu_gsp_isr_support(struct gk20a *g, struct nvgpu_gsp *gsp, bool enable)
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{
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nvgpu_log_fn(g, " ");
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/* Enable irq*/
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nvgpu_mutex_acquire(&gsp->isr_mutex);
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if (g->ops.gsp.enable_irq != NULL) {
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g->ops.gsp.enable_irq(g, enable);
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}
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gsp->isr_enabled = enable;
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nvgpu_mutex_release(&gsp->isr_mutex);
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}
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void nvgpu_gsp_suspend(struct gk20a *g, struct nvgpu_gsp *gsp)
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{
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nvgpu_gsp_isr_support(g, gsp, false);
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#ifdef CONFIG_NVGPU_FALCON_DEBUG
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nvgpu_falcon_dbg_error_print_enable(gsp->gsp_flcn, false);
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#endif
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}
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void nvgpu_gsp_sw_deinit(struct gk20a *g, struct nvgpu_gsp *gsp)
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{
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if (gsp != NULL) {
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nvgpu_mutex_destroy(&gsp->isr_mutex);
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#ifdef CONFIG_NVGPU_FALCON_DEBUG
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nvgpu_falcon_dbg_buf_destroy(gsp->gsp_flcn);
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#endif
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nvgpu_kfree(g, gsp);
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gsp = NULL;
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}
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}
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int nvgpu_gsp_debug_buf_init(struct gk20a *g, u32 queue_no, u32 buffer_size)
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{
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int err = 0;
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nvgpu_log_fn(g, " ");
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/* enable debug buffer support */
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#ifdef CONFIG_NVGPU_FALCON_DEBUG
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if ((g->ops.gsp.gsp_get_queue_head != NULL) &&
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(g->ops.gsp.gsp_get_queue_tail != NULL)) {
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err = nvgpu_falcon_dbg_buf_init(
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&g->gsp_flcn, buffer_size,
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g->ops.gsp.gsp_get_queue_head(queue_no),
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g->ops.gsp.gsp_get_queue_tail(queue_no));
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if (err != 0) {
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nvgpu_err(g, "GSP debug init failed");
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}
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}
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#else
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(void)queue_no;
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(void)buffer_size;
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#endif
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return err;
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}
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void nvgpu_gsp_isr_mutex_acquire(struct gk20a *g, struct nvgpu_gsp *gsp)
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{
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(void)g;
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nvgpu_mutex_acquire(&gsp->isr_mutex);
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}
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void nvgpu_gsp_isr_mutex_release(struct gk20a *g, struct nvgpu_gsp *gsp)
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{
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(void)g;
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nvgpu_mutex_release(&gsp->isr_mutex);
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}
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bool nvgpu_gsp_is_isr_enable(struct gk20a *g, struct nvgpu_gsp *gsp)
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{
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(void)g;
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return gsp->isr_enabled;
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}
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struct nvgpu_falcon *nvgpu_gsp_falcon_instance(struct gk20a *g)
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{
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return &g->gsp_flcn;
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}
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void nvgpu_gsp_isr(struct gk20a *g)
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{
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#ifdef CONFIG_NVGPU_GSP_STRESS_TEST
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if (nvgpu_gsp_get_stress_test_load(g)) {
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nvgpu_gsp_stest_isr(g);
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return;
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}
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#endif
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#ifdef CONFIG_NVGPU_GSP_SCHEDULER
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nvgpu_gsp_sched_isr(g);
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#endif
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return;
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}
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