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9907b97985
Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the ce2 sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I7dfd5e8dcd4d6f3623d1b795b6b2e15ff356a13a Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1509632 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
73 lines
2.1 KiB
C
73 lines
2.1 KiB
C
/*
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* Pascal GPU series Copy Engine.
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*
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* Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program.
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*/
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#include "gk20a/gk20a.h"
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#include "ce_gp10b.h"
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#include <nvgpu/hw/gp10b/hw_ce_gp10b.h>
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static u32 ce_blockpipe_isr(struct gk20a *g, u32 fifo_intr)
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{
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gk20a_dbg(gpu_dbg_intr, "ce blocking pipe interrupt\n");
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return ce_intr_status_blockpipe_pending_f();
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}
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static u32 ce_launcherr_isr(struct gk20a *g, u32 fifo_intr)
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{
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gk20a_dbg(gpu_dbg_intr, "ce launch error interrupt\n");
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return ce_intr_status_launcherr_pending_f();
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}
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void gp10b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
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{
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u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id));
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u32 clear_intr = 0;
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gk20a_dbg(gpu_dbg_intr, "ce isr %08x %08x\n", ce_intr, inst_id);
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/* clear blocking interrupts: they exibit broken behavior */
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if (ce_intr & ce_intr_status_blockpipe_pending_f())
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clear_intr |= ce_blockpipe_isr(g, ce_intr);
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if (ce_intr & ce_intr_status_launcherr_pending_f())
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clear_intr |= ce_launcherr_isr(g, ce_intr);
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gk20a_writel(g, ce_intr_status_r(inst_id), clear_intr);
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return;
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}
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int gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
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{
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int ops = 0;
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u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id));
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gk20a_dbg(gpu_dbg_intr, "ce nonstall isr %08x %08x\n", ce_intr, inst_id);
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if (ce_intr & ce_intr_status_nonblockpipe_pending_f()) {
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gk20a_writel(g, ce_intr_status_r(inst_id),
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ce_intr_status_nonblockpipe_pending_f());
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ops |= (gk20a_nonstall_ops_wakeup_semaphore |
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gk20a_nonstall_ops_post_events);
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}
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return ops;
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}
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